The Buffer Control Chip Chip (BCC)

• LVDS buffering
• 40 MHZ BCO clock multiplier to get a 80 MHz DCLK
• Config register, with readback
• ABCN DCLK selectable as 40/80 MHz
• Multiplexes

• All clock signals are derived from the BCO input.
• The power-on reset disables the chip for 512 cycles of the BCO clock.
• Each BCC has a hardware address that can be set on the ID0-ID5 inputs.
• The BCC includes a header in the commands forwarded to the ABCN chips are . The BCC(s) concerned by this header forwards the payload to the ABCNs.
• It de-multiplexes the L1R signal into the reset and trigger signals.

BCC configuration

with BCC

The BCC chip implements a clock multiplier for 80 MHz readout and multiplexing of two data streams onto a 80/160 MHz data line (depending on the data clock frequency). It has a 16-bit configuration register which is writable though the command line and remains unaffected by a reset through the L1R line. The meaning of each bit is shown below.

• All clock signals are derived from the BCO input.
• The power-on reset disables the chip for 512 cycles of the BCO clock.
• Each BCC has a hardware address that can be set on the ID0-ID5 inputs.
• The BCC includes a header in the commands forwarded to the ABCN chips are . The BCC(s) concerned by this header forwards the payload to the ABCNs.
• It de-multiplexes the L1R signal into the reset and trigger signals.

Checking the BCC configuration

Setting delays

mode	Quad	r80	iSCLK	iACLK	iBCO	iDCLK	eACLK	eBCO	eDCLK	sCOL0	sCOL1	CDM	b80
0	0	1	1	1	0	0	1	1	1	0	0	0	0

-- SergioGonzalez - 28-Jun-2011