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The Buffer Control Chip Chip (BCC)

The BCC chip receives as input the main BCO clock @40 MHz and it can deliver a 80 MHz DCLK. It then multiplexes the data coming from the two columns of one hybrid onto a 80/160 MHz data line (depending on the DCLK frequency selected, 40/80 MHz). The BCC has a 5-bit hardware address and one can perform read/write operations on its 16-bit configuration register. The BCC also receives a L1R signal which is de-multiplexed into the reset (RESETB) and trigger (L1) signals to be delivered to the ABCN chips. After a power-reset, the chip is disabled for 512 cycles of the BCO clock.

Some documentation and related links:

  • All clock signals are derived from the BCO input.
  • The BCC includes a header in the commands forwarded to the ABCN chips are . The BCC(s) concerned by this header forwards the payload to the ABCNs.

Config register, with read-back ABCN data clock (DCLK) selectable as 40 or 80MHz Multiplex 2 ABCN streams onto 80/160MHz data line L1 line multiplexed with RESETB (L1R) – separate decoder, provides BCC-RESET Programmable Clocks inversion ABCN data sync (“sample and hold”) (invertible) ABCN signals synchronised to BCO (invertible) No-MUX mode – single channel readout select Redundant ABCN data lines selectable Power-on Reset Quad-mode – mux all 4 data lines (low priority feature)

BCC configuration

with BCC

The BCC chip implements a clock multiplier for 80 MHz readout and multiplexing of two data streams onto a 80/160 MHz data line (depending on the data clock frequency). It has a 16-bit configuration register which is writable though the command line and remains unaffected by a reset through the L1R line. The meaning of each bit is shown below.

  • All clock signals are derived from the BCO input.
  • The power-on reset disables the chip for 512 cycles of the BCO clock.
  • Each BCC has a hardware address that can be set on the ID0-ID5 inputs.
  • The BCC includes a header in the commands forwarded to the ABCN chips are . The BCC(s) concerned by this header forwards the payload to the ABCNs.
  • It de-multiplexes the L1R signal into the reset and trigger signals.

Checking the BCC configuration

bit Meaning Possible values Default value
15 unused - -
14 - - -
13 - - -
12 - - -
11 - - -
10 DCLK enable - -
9 BCO enable - -
8 ACLK enable - -
7 DCLK invert - -
6 BCO - -
5 ACLK invert - -
4 SCLK invert - -
3 80 MHz readout select - -
2 Quad mode select - -
[0,1] Data MUX select source 0,1,2,3 0

Setting delays

mode Quad r80 iSCLK iACLK iBCO iDCLK eACLK eBCO eDCLK sCOL0 sCOL1 CDM b80
0 0 1 1 1 0 0 1 1 1 0 0 0 0

-- SergioGonzalez - 28-Jun-2011

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PDFpdf BCC-Thesis.pdf r1 manage 2197.2 K 2011-06-30 - 13:31 SergioGonzalez  
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Topic revision: r4 - 2011-06-30 - SergioGonzalez
 
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