The usual 2 years alternating Tick-Tock model of Intel's processor production has now changed to a more 3-4 years oriented model. The shrinkage of feature sizes is essentially delayed and e.g. the 14nm process has now two 'extensions' (14nm+ and 14nm++). http://marketrealist.com/2017/03/its-official-intel-will-bring-a-4th-processor-on-its-14nm-node/

Technology details about the upcoming 10nm process can be found here: http://techreport.com/review/31660/intel-defends-its-process-technology-leadership-at-14nm-and-10nm/2

The latest report of the ITRS (May 2016) predicts that the shrinking of the feature size on chips will have economical limits. http://spectrum.ieee.org/semiconductors/devices/transistors-could-stop-shrinking-in-2021

  • ITRS_prediction_gate_schrinking_May2016.png:
    ITRS_prediction_gate_schrinking_May2016.png

The production node-names (e.g. 22nm 14nm etc.) are since the 65nm process technology not anymore representing the real feature sizes on the silicon, but are rather production names. And these names represent different technologies for the 4 main foundries (INTEL, TSMC, Globalfoundrie and SAMSUNG). http://www.extremetech.com/computing/221532-tsmc-will-begin-10nm-production-this-year-claims-5nm-by-2020 The following table shows the real feature sizes for the production name:

  • feature_size_comparison.png:
    feature_size_comparison.png

https://www.semiwiki.com/forum/content/6590-scott-jones-iss-talk-moores-law-lives.html?new_comment= cpu_feature_sizes_Feb2017.JPG standard_cell_feature_sizes.JPG

The difference in node name and feature sizes can be seen also in the flowing plots from an INTEL talk at the Intel-Developer-Forum in autumn 2016. http://electroiq.com/chipworks_real_chips_blog/2017/01/25/intels-10nm-enigma/

  • Gate-pitch_intel.png: * Cell-size_intel.png: * Cell-size-2_intel.png:

Gate-pitch_intel.png Cell-size_intel.png Cell-size-2_intel.png

16. Aug 2017 schedule of Ice Lake from Intel, 10nm process https://www.extremetech.com/computing/254209-details-leak-intels-upcoming-ice-lake-cpu-10nm-schedule

  • intel_ice_lake_10nm_Slide1.png:
    intel_ice_lake_10nm_Slide1.png

  • intel_ice_lake_10nm_Slide2.png:
    intel_ice_lake_10nm_Slide2.png

  • intel_ice_lake_10nm_Slide3.png:
    intel_ice_lake_10nm_Slide3.png

  • intel_ice_lake_10nm_Slide4.png:
    intel_ice_lake_10nm_Slide4.png

  • intel_ice_lake_10nm_Slide5.png:
    intel_ice_lake_10nm_Slide5.png

  • intel_ice_lake_10nm_Slide6.png:
    intel_ice_lake_10nm_Slide6.png

  • intel_ice_lake_10nm_Slide7.png:
    intel_ice_lake_10nm_Slide7.png
Topic attachments
I Attachment History Action Size Date Who Comment
PNGpng Cell-size-2_intel.png r1 manage 99.5 K 2017-01-26 - 15:28 BerndPanzerSteindel  
PNGpng Cell-size_intel.png r1 manage 96.1 K 2017-01-26 - 15:27 BerndPanzerSteindel  
PNGpng Gate-pitch_intel.png r1 manage 78.8 K 2017-01-26 - 15:26 BerndPanzerSteindel  
PNGpng ITRS_prediction_gate_schrinking_May2016.png r1 manage 26.0 K 2017-01-26 - 15:05 BerndPanzerSteindel  
JPEGjpg cpu_feature_sizes_Feb2017.JPG r1 manage 52.7 K 2017-05-12 - 08:09 BerndPanzerSteindel  
PNGpng feature_size_comparison.png r1 manage 137.7 K 2017-01-26 - 15:12 BerndPanzerSteindel  
JPEGjpg standard_cell_feature_sizes.JPG r1 manage 37.5 K 2017-05-12 - 08:13 BerndPanzerSteindel  
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Topic revision: r4 - 2017-09-24 - BerndPanzerSteindel
 
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