1 Introduction

2 Design Status Update:

3 Hardware

3.1 CaR Board

CaR Board V0.1

CaR board is designed for the operation of 2 FEI4 boards, each FEI4 board can have the following resources:

  • Power resource
    • 5 adjustable(0.8 ~ 3.0V), monitored power rails, the maximum current capability is 500 mA;
    • One fixed(can be adjusted by modifying the resistors) monitored 1.8V power rail, the maximum current capability is 1A;
  • Bias resource
    • 8 channel adjustable(0.8 ~ 3.0V) bias, output current load capability is 20 mA;
  • Control signals
    • Input(to FEI4 board)
      • LVCMOS 1.8V 4
      • LVCMOS 1.5V 1
    • Output(from FEI4 board)
      • LVCMOS 1.2V 1
      • LVCMOS 1.5V 1
  • Injection signal
    • One channel, pulse width/height adjustable(0~3.0V)
  • LVDS signals
    • 2 pairs of LVDS 2.5V
  • Clock
    • 40MHz LVDS 2.5V clock from clock buffer CDCLVD1204
  • Analog digitizable channel
    • 3 channels, with sampling rate at 40MHz, signal input range can be adjusted by modifying the gain of the ADC driver

Figure 1. Top side of CaR Board V0.1

Design Files

Issues identified

  1. The I2C address for the current monitor located at 0x47 is conflicting with the broad cast I2C address of the DAC7678s on board.
  2. ADC DCLK and DATA signals are not routed into the same FPGA bank.
  3. The enable signal of the I2C differential buffer is connected to the output of IO expander, this signal need to be pulled up to VCC.

CaR Board V0.2

CaR Board has been revised to V0.2 already but has not been sent out for fabrication yet.

Design Files

3.2 FEI4 board

FEI4 Board V0.1

Design files

FEI4 Board V0.2

Revision list from FEI4 Board V0.1 to V0.2:

  1. FEI4 is moved to the higher side;
  2. PCIE mini connector is moved to the lower side;
  3. RJ45 signal mapping is corrected;
  4. All the signal connectors are replaced with LEMO;
  5. Board cut out area is enlarged for the convenience of wire bonding;
  6. SEAF connectors are replaced with a normal one instead of the original right angle one for lab test;
  7. Solder Mask under the FEI4 is removed;

Figure 2. FEI4 board V0.2 with CCPD board V0.2 attached

Design Files

3.3 CCPD Board

The CCPD board is connected to the FEI4 board through the PCIE mini connector, the CCPD board can have the following resources from FEI4 board:

  • Power
    • VCC fixed at 3.3V
    • 3 adjustable(0.8 ~ 3.0V), monitored power rails, the maximum current capability is 500 mA;
  • Bias
    • 8 channel adjustable(0.8 ~ 3.0V) bias, output current load capability is 20 mA;
  • Control signals
    • Input(to FEI4 board)
      • LVCMOS 1.8V 4
      • LVCMOS 1.5V 1
    • Output(from FEI4 board)
      • LVCMOS 1.5V 1
  • High Voltage from the LEMO connector on FEI4 board
  • Analog digitizable channel
    • 3 channels, with sampling rate at 40MHz, signal input range can be adjusted by modifying the gain of the ADC driver

CCPD Board V0.1

Design Files

Issues identified

  1. The offset of PCIe golden finger on the top edge is not correct;
  2. Bonding pads are too close to the edge of the cut out of the FEI4 board;

CCPD Board V0.2

Figure 3. Top side of the CCPD board V0.2

Figure 4. Bottom side of the CCPD board V0.2

Design Files

3.4 VHDCI Adapter Cards

3.4.1 FMC to VHDCI Adapter Card

Figure 5. FMC to VHDCI Adapter Card

Design Files

3.4.2 VHDCI to FMC Adapter Card

Figure 6. VHDCI to FMC Adapter Card

Design Files

Issues identified

  1. The enable of the I2C buffer PCA9614 is controlled by the IO expander PCA9539, the default output of the PCA9539 is '0'. This will make the I2C bus can't work before the PCA9539 is configured properly through I2C bus.
    Currently, we are using a wire connect this net to VCC on the VHDCI2FMC board (Pull up).

4 Firmware

The firmware of CaRIBO u is uploaded to the GitHub repository:

https://github.com/liuhb08/Caribou-FW

5 Software

The software of CaRIBOu system is uploaded to the GitLab repository:

https://gitlab.cern.ch/Caribou/Caribou-SW

Topic attachments
I Attachment History Action Size Date Who Comment
PDFpdf CARIBOu_Hardware_design_status_and_plan.v3.pdf r1 manage 890.2 K 2015-11-19 - 01:55 HongbinLiu  
PDFpdf CCPD_Board_V0.2_Bonding_Guidelines.pdf r1 manage 105.3 K 2015-11-23 - 17:28 HongbinLiu  
Unknown file formatxlsx CCPD_Board_V02.xlsx r1 manage 13.0 K 2015-11-19 - 03:06 HongbinLiu  
Compressed Zip archivezip CCPD_Board_V1_Gerber.zip r1 manage 128.6 K 2015-11-12 - 18:24 HongbinLiu  
Unknown file formatpcb CCPD_Board_V1_Layout.pcb r1 manage 569.2 K 2015-11-12 - 18:24 HongbinLiu  
PDFpdf CCPD_Board_V1_Schematic.pdf r1 manage 53.6 K 2015-11-12 - 18:24 HongbinLiu  
Compressed Zip archivezip CCPD_Board_V2_Gerber.zip r1 manage 123.2 K 2015-11-12 - 18:06 HongbinLiu  
Unknown file formatpcb CCPD_Board_V2_Layout.pcb r1 manage 632.6 K 2015-11-12 - 18:06 HongbinLiu  
PDFpdf CCPD_Board_V2_Schematic.pdf r1 manage 76.5 K 2015-11-12 - 18:06 HongbinLiu  
PDFpdf CaRIBOuDesign_20150702.pdf r1 manage 1675.3 K 2015-11-19 - 02:01 HongbinLiu  
PDFpdf CaRIBOu_design_status_update_20150831.pdf r1 manage 1690.2 K 2015-11-12 - 17:40 HongbinLiu  
PDFpdf CaRIBOu_design_status_update_20151117.v2.pdf r1 manage 959.7 K 2015-11-23 - 20:18 HongbinLiu  
Unknown file formatxlsx CaR_Board_V01.xlsx r1 manage 22.0 K 2015-11-19 - 03:06 HongbinLiu  
Compressed Zip archivezip CaR_Board_V1_Gerber.zip r1 manage 675.3 K 2015-11-12 - 17:51 HongbinLiu  
Unknown file formatpcb CaR_Board_V1_Layout.pcb r1 manage 2800.2 K 2015-11-12 - 17:52 HongbinLiu  
PDFpdf CaR_Board_V1_Schematic.pdf r1 manage 449.5 K 2015-11-12 - 17:52 HongbinLiu  
Compressed Zip archivezip CaR_Board_V2_Gerber.zip r1 manage 720.8 K 2015-11-12 - 20:32 HongbinLiu  
Unknown file formatpcb CaR_Board_V2_Layout.pcb r1 manage 3264.1 K 2015-11-12 - 20:32 HongbinLiu  
PDFpdf CaR_Board_V2_Schematic.pdf r1 manage 834.8 K 2015-11-12 - 20:32 HongbinLiu  
Unknown file formatxlsx FEI4_Board_V02.xlsx r1 manage 16.3 K 2015-11-19 - 03:06 HongbinLiu  
Compressed Zip archivezip FEI4_Board_V1_Gerber.zip r1 manage 280.7 K 2015-11-12 - 18:24 HongbinLiu  
Unknown file formatpcb FEI4_Board_V1_Layout.pcb r1 manage 913.3 K 2015-11-12 - 18:24 HongbinLiu  
PDFpdf FEI4_Board_V1_Schematic.pdf r1 manage 142.9 K 2015-11-12 - 18:24 HongbinLiu  
Compressed Zip archivezip FEI4_Board_V2_Gerber.zip r1 manage 325.4 K 2015-11-12 - 18:06 HongbinLiu  
Unknown file formatpcb FEI4_Board_V2_Layout.pcb r1 manage 3026.2 K 2015-11-12 - 18:06 HongbinLiu  
PDFpdf FEI4_Board_V2_Schematic.pdf r1 manage 280.3 K 2015-11-12 - 18:06 HongbinLiu  
PDFpdf FEI4_Board_Ver_0.2_Bonding_Guidelines.pdf r1 manage 686.6 K 2015-11-23 - 15:52 HongbinLiu  
PDFpdf FEI4_Board_Ver_0.2_Bonding_Scheme_V2.pdf r1 manage 295.6 K 2015-11-23 - 15:49 HongbinLiu  
Unknown file formatxlsx FMC2VHDCI_V01.xlsx r1 manage 12.7 K 2015-11-19 - 03:06 HongbinLiu  
Compressed Zip archivezip FMC_to_VHDCI_Adapter_Board_Gerber.zip r1 manage 188.8 K 2015-11-12 - 18:48 HongbinLiu  
Unknown file formatpcb FMC_to_VHDCI_Adapter_Board_Layout.pcb r1 manage 706.2 K 2015-11-12 - 18:48 HongbinLiu  
PDFpdf FMC_to_VHDCI_Adapter_Board_Schematic.pdf r1 manage 94.3 K 2015-11-12 - 18:48 HongbinLiu  
Unknown file formatxlsx VHDCI2FMC_V01.xlsx r1 manage 12.4 K 2015-11-19 - 03:06 HongbinLiu  
Unknown file formatpcb VHDCI_to_FMC_Adapter_Board_Layout.pcb r1 manage 712.2 K 2015-11-12 - 18:48 HongbinLiu  
PDFpdf VHDCI_to_FMC_Adapter_Board_Schematic.pdf r1 manage 87.6 K 2015-11-12 - 18:48 HongbinLiu  
Compressed Zip archivezip VHDCI_to_FMC_Adapter_Board__Gerber.zip r1 manage 186.9 K 2015-11-12 - 18:48 HongbinLiu  
JPEGjpg car_v01_pic.jpg r1 manage 140.8 K 2015-11-19 - 02:34 HongbinLiu  
PNGpng ccpd_board_v02_bot.png r1 manage 208.7 K 2015-11-23 - 20:09 HongbinLiu  
PNGpng ccpd_board_v02_top.png r1 manage 270.9 K 2015-11-23 - 20:09 HongbinLiu  
PNGpng fei4_v02_ccpd_v02_pic.png r1 manage 463.7 K 2015-11-19 - 02:42 HongbinLiu  
PNGpng fmc_to_vhdci_v01_pic.png r1 manage 492.8 K 2015-11-23 - 20:13 HongbinLiu  
PNGpng vhdci_to_fmc_v01_pic.png r1 manage 567.5 K 2015-11-23 - 20:13 HongbinLiu  
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Topic revision: r12 - 2015-12-02 - MathieuB
 
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