My Notes



People and their vacations

LIP Vacations Table

Software

Reyes' presentations in Indico, Pasquale's presentations in Indico, Pedro's Wiki ECAL Meetings

Installing XDAQ and TriDAS ECAL CVS

Show... Hide

XDAQ files at Sourceforge and detailed Installation instructions

tar -zxf coretools_G_17559_V3_5_2.tgz

tar --exclude ./TriDAS/config -zxf powerpack_G_28175_V1_4_3.tgz

tar --exclude ./TriDAS/daq/Makefile -zxf worksuite_G_28176_V1_5_1.tgz

export XDAQ_ROOT=`pwd`/TriDAS

make -C $XDAQ_ROOT/daq Set=extern

make -C $XDAQ_ROOT/daq Set=coretools

make -C $XDAQ_ROOT/java Set=xdaq3

make -C $XDAQ_ROOT/daq Set=powerpack

make -C $XDAQ_ROOT/daq Set=worksuite

# CAEN driver "instructions" here

wget -P /tmp http://cmsdoc.cern.ch/~cschwick/software/distribution/CAEN/CAENVME_v2-4_CMS-02.tgz

cd /tmp && tar -xzvf /tmp/CAENVME_v2-4_CMS-02.tgz

cd /tmp/CAENVME

su root

./installCAEN.pl

(say yes to questions)

cd /usr/local/CAEN/CAENVME-Rev2.4/Linux/driver/v2718/

chmod +x a2818_load.`uname -r | cut -b-3` && ./a2818_load.`uname -r | cut -b-3`

(add to /etc/rc.d/rc.local)

# SBS driver "instructions" here

wget -P /tmp http://cmsdoc.cern.ch/~cschwick/software/distribution/SBS/SBS_v2p3p0_CMS-01.tgz

cd /tmp && tar -xzvf /tmp/SBS_v2p3p0_CMS-01.tgz

cd /tmp/SBS

su root

ln -sf /usr/src/linux-2.4 /usr/src/linux && rm -rf /usr/local/SBS

./installSBS

(say yes to questions)

/usr/local/SBS/1003/v2p3p0/sys/mkbtp

(add to /etc/rc.d/rc.local)

#HAL (9000?)

cd $XDAQ_ROOT/daq/hal

./configure.pl && make

#Fedkit

make -C $XDAQ_ROOT/daq/itools/

#PHeaps

make -C $XDAQ_ROOT/daq/pheaps/

make -C $XDAQ_ROOT/daq/pheaps/drv/bigphys/

su

make -C $XDAQ_ROOT/daq/pheaps/drv/bigphys/ load

(add to /etc/rc.d/rc.local and add bigphysarea=131072 in /etc/grub.conf)

cd $XDAQ_ROOT

cvs -d ":kserver:isscvs.cern.ch:/local/reps/tridas" co ecal

#project TriDAS && cvs co ecal

cd $XDAQ_ROOT/ecal/config

./makenv.sh

source env.sh

make -C $XDAQ_ROOT/ecal/gconfig install

for package in ecalBase ecalCommonTools ecalRootTools ecalDB ecalDataDecoder; do make -C $XDAQ_ROOT/ecal/$package; done

for package in ecalCrateScanner ecalDCC ecalSLB ecalDCCTester ; do make -C $XDAQ_ROOT/ecal/$package all; done

Configuration tips

  • Edit $XDAQ_ROOT/daq/xdaq/etc/profile.xml and in the Executive replace DEBUG with INFO or run xdaq with log level INFO, DEBUG, WARN or ERROR by appending the -l LOGLEVEL option
  • (not working with new CVS server) RSS feed of the CMS CVS server at http://cmsdoc.cern.ch/swdev/cvsserver/rss/TriDAS@ecal.rss (repository@moduleNOSPAMPLEASE.rss)
  • If using bash and an afs CERN account in the zh group, include source /afs/cern.ch/cms/sw/cmsset_default.sh to your ~/.bashrc

Databases

  • After source /etc/hepix/oracle_env.sh or source /afs/cern.ch/project/oracle/script/setoraenv.sh -s 10102gcc323 and export NLS_LANG= one can use sqlplus test04|cond01|read04/ora@ecalh4db
  • The TNS to hostname translation is at /afs/cern.ch/project/oracle/admin/tnsnames.ora
  • From ROOT one can use s = TSQLServer::Connect("oracle://pccmsecdb.cern.ch/ecalh4db","test04","ora")
  • how to store TH1S in a BLOB ?!

DAQ links

CMS Wiki, TriDAS, XDAQ, XDAQ Coretools API, HAL Documentation, HAL API, Quick Reference for CVS (from xdaqwiki), CMS CVS Repository, TriDAS CVS, Ecal CVS, RU builder, RU Builder Manual, DAQKit, RCMS - Run Control CMSSW

How to use XDAQ path expansion and remote files

Hardware

People:

  • Ze Carlos and Michal

Programming of the boards without a cable

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Crucial for a running experiment, since there are 12*3*( 1 DCC + 1 CCS + 1 TCC68 )+6*3*( 1 DCC + 1 CCS + 4 TCC48 ) = 216 boards, out of which 54 DCCs.

MTM

Nuno Cardoso started working on a board to do that using the MTM part of the VME64 bus. This guarantees compatibility with all boards in the ECAL but it requires a lot of work and the production of the corresponding boards.

VME bridge + software

Software for programming FPGAs

Jam vs. SVF

To have an idea of what Jam and SVF look like for the same thing (from the Altera site):

TRST ABSENT;
ENDDR IDLE;
ENDIR IDLE;
STATE IDLE;
SIR 10 TDI (00D);
SDR 13646 TDI (...);
STATE RESET;
STATE IDLE;

The first line denotes that the TRST pin is unused. The two subsequent lines prompt the SVF parser to bring the JTAG state machine back to IDLE state after every instruction and data. The I/O reconfiguration process starts in IDLE state and proceed to execute the CONFIG_IO instruction (with code 00D). This is followed by the long IOCSR data being shifted in (shown by “…”). Since there is no more JTAG instruction follows, a cycle through the RESET state and back to IDLE state is executed.

The algorithm is very straight forward and simple. The user can copy and embed this routine into any existing SVF-based test routines to perform I/O reconfiguration.

NOTE MAX_FREQ "10000000";
ACTION CONFIG_IO = EXECUTE;
PROCEDURE EXECUTE;
BOOLEAN X = 0;
DRSTOP IDLE;
IRSTOP IDLE;
STATE IDLE;
IRSCAN 10, $00D;
DRSCAN 13646,
$...;
STATE RESET;
STATE IDLE;
EXIT 0;
ENDPROC;

The first line denotes that the recommended maximum frequency for TCK is 10MHz. The action name for I/O reconfiguration procedure is “CONFIG_IO”. The rest is the same as stated in “Using SVF Output File” section.

Again, the user can copy and embed this procedure into any existing JAM-based test routines to perform I/O reconfiguration. To use it with Altera’s JAM Player, type: jam –aCONFIG_IO .jam

Hardware

The JTAG scan bridge used is the SCANSTA111. It provides 3 chains:

  • Chain 0 goes to Boundary scan of all other components + the VME bridge Altera FPGA
  • Chain 1 goes to the Alteras
  • Chain 2 goes to the Xilinxs
  • The S0-4 pins are connected to the MTM ID (active low: board 1 has ID 0x1e); S5-6 are grounded

Geographical addressing (based on ANSI/VITA 1.1-1997)

VME slot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Address on the SCANSTA 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A
 
EB CAEN     TCC68 CCS DCC     TCC68 CCS DCC     TCC68 CCS DCC    
Address 0x1E       0x1A 0x19 0x18       0x14 0x13 0x12       0x0E 0x0D 0x0C    
 
EE CAEN TCC48 TCC48 TCC48 TCC48 CCS DCC TCC48 TCC48 TCC48 TCC48 CCS DCC TCC48 TCC48 TCC48 TCC48 CCS DCC    
Address 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C    

The VME bridge FPGA is connected to the scan bridge in the DCC. stop.gif That is not the case in the TCC48s.

The JTAG chain B (backplane) of the scan bridge can be accessed via the VME board address, offset 0x000744, where the 32-bit register maps to:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused TRST TCKMask[7..0] TMS[7..0] TDI/TDO[7..0]

  • TRST - Maps to the TRST input of the scan bridge. Writing a one keeps the TRST high for XX microseconds.
  • TCKMask - 8 bit mask defining which of the bits in the TMS and TDI are valid. The state machine will shift from the LSB and stop as soon as it sees a 0 in this mask, therefore subsequent one are ignored.
  • TMS and TDI - 8 bit fields with the JTAG information to be shifted
  • TDO - After a write operation (with Enable=1), a read operation puts the TDO bits such that the MSB is the first bit shifted out.

Operations available on 0x000744:

  • To shift 8 bits into the JTAG chain write 0x00.ff.xx.yy, where xx ( yy) are 8 TMS (TDI) bits. Reading the register after this will return 0x80.ff.xx.zz, where zz are the 8 TDO bits from the chain.
  • To write fewer than 8 bits, define a mask using the TCKMask field (e.g. 0x01, 0x03, 0x07, 0x0f, 0x1f, etc)
  • To reset the scan bridge to its default state (and possibly address a different chain) TRST needs to be asserted. This can be done by writing 0x01.00.00.00

Steps

  1. Define register in VME bridge and protocol done.gif
  2. Route register bits to JTAG lines and cycle TCK only on write access done.gif (JCS)
  3. Route EvBuilder LED to activity in JTAG register led-red.gif (JCS)
  4. Test access to register with HAL done.gif (AD)
  5. Check correct activity on JTAG lines done.gif
  6. Connect LEDs to Y0 (pin 30) and Y1 (pin 41) led-red.gif
  7. Test selection of individual ports with HAL done.gif (AD)
  8. Develop interface to existing programming software done.gif (AD)
  9. Define bitfile format for programming of the chains done.gif (JCS)
  10. Test programming FPGAs through individual ports with HAL done.gif (AD)
  11. Extend to Xilinx done.gif
  12. Solve the Altera Eprom programming problem wip.gif
  13. Interface with ECAL Supervisor and CMS databases todo.gif (AD)
  14. Test parallel programming of boards in the same crate todo.gif (AD)

USC55

Links: Level 1, Crates and racks, ECAL Elog

DCC, TCC and SRP codes

From ECAL raw data format v1.5:

DCC
bits int description
0000 0 Channel enabled and no errors identified
0001 1 Channel disabled by configuration
0010 2 Data present timeout
0011 3 FE Header mismatch
0100 4 FE Tower identifier mismatch
0101 5 Channel Link Error
0110 6 Number of words received mismatch
0111 7 Channel data suppressed by filtering
1000 8 Input FIFO full
10xx 9/10/11 Synchronization error when at least one bit in xx is enabled (bit0: L1A Event number, bit 1: Bunch Crossing number )
1100 12 Input FIFO full condition while L1A still needs to be processed
11xx 13/14 Parity error when at least one bit in xx is enabled ( bit 0: horizontal, bit 1: vertical )
1111 15 Channel data readout with forced ZS level 1

TCC
bits int description
000 0 Low interest TT (Et below low threshold)
001 1 Mid-interest TT (Et between low and high thresholds)
010 2 Not used
011 3 High-interest TT (Et above high threshold)
100 4 Force TT readout (Agilent sync link error or Hamming error)
101 5 Not used
11x 6/7 Not used

SRP
bits int description
000 0 Suppress FE channel
001 1 Read FE channel with level 1 zero suppression threshold
010 2 Read FE channel with level 2 zero suppression threshold
011 3 Read FE channel without zero suppression
1xx 4/5/6/7 xx action has been forced by an error condition or by configuration

Overview

Rack Slot PC Serial Model PC name Alias CAEN SN CAEN Link Crate
42-37 Empty
36 Vent PDU
35 PDU
34   R410 srv-s2f19-34-01 ecalod-disk01, ecalod-web01      
31   R620 srv-s2f19-31-01 ecalod-newled-ctrl      
33-32 Empty
30   R620 srv-s2f19-30-01 ecalod-xmas      
29   R620 srv-s2f19-29-01 ecalod-dqm      
28   R620 srv-s2f19-28-01 ecalod-evb      
27   R620 srv-s2f19-27-01 ecalod-daq      
26   R620 srv-s2f19-26-01 esod-evb      
25   R620 srv-s2f19-25-01 esod-daq      
24 Vent PDU
23 PDU
22-20 Empty
19 JDYL R320 vmepc-s2f19-19-01 ecalod-srp 278 0 S2D05J(or H)
ecalod-ttcf 1 S2D05G(or E)
18 C20M R320 vmepc-s2f19-18-01 ecalod-eep 276 0 S2D06L
1 S2D02L
2 S2D07L
17 4FYL R320 vmepc-s2f19-17-01 ecalod-ebp2 275 0 S2D07H
1 S2D08H
2 S2D06H
16 FZZL R320 vmepc-s2f19-16-01 ecalod-ebp1 274 0 S2D04H
1 S2D02H
2 S2D03H
15 500M R320 vmepc-s2f19-15-01 ecalod-ebm2 273 0 S2D07D
1 S2D08D
2 S2D06D
14 JDZL R320 vmepc-s2f19-14-01 ecalod-ebm1 272 0 S2D04D
1 S2D02D
2 S2D03D
13 HZYL R320 vmepc-s2f19-13-01 ecalod-eem 271 0 S2D04L
1 S2D03L
2 S2D08L
12 Vent PDU
11 PDU
10-9 Empty
8 JZYL R320 vmepc-s2f19-08-01 ecalod-spare 270 0 S2D01H
7 7DZL R320 vmepc-s2f19-07-01 esod-esp 269 0 S1C00D (PR)
1 S1C00G (PF)
6 80ZL R320 vmepc-s2f19-06-01 esod-esm 268 0 S1D00D (MR)
1 S1D00G (MF)

| Name | Short | Crate | FED | FEDs | Con | Geo | Partition | Note | Caen PCI fw | LHC crate | Model | Note |
EE-
vmepcS2F19-01 Green led ecalod-01 ecalod-S2D04l ecalfed-601 609 601 602 D3 D3 D3 -06 -07* -08* ecalod-EEm1   todo.gif 7185 0022 SC1425 DONE
vmepcS2F19-02 Green led ecalod-02 ecalod-S2D03l ecalfed-603 603 604 605 D3 D4 D4 -09 -01 -02* ecalod-EEm2   todo.gif 7185 0021 SC1425 DONE
vmepcS2F19-03 Green led ecalod-03 ecalod-S2D08l ecalfed-606 606 607 608 D4 D4 D4/3 -03* -04 -05 ecalod-EEm3   todo.gif 7185 0008 SC1425 DONE
EB-
vmepcS2F19-04 Green led ecalod-04 ecalod-S2D04d ecalfed-610 610 611 612 24 22 13 -01 -02 -03 ecalod-EBm1 A2818:0.8 7185 0014 SC1425 DONE
vmepcS2F19-05 Green led ecalod-05 ecalod-S2D02d ecalfed-613 613 614 615 31 26 16 -04 -05 -06 ecalod-EBm2 A2818:0.8 7185 0018 SC1425 DONE
vmepcS2F19-06 Green led ecalod-06 ecalod-S2D03d ecalfed-616 616 617 618 02 11 05 -07 -08 -09 ecalod-EBm3 A2818:0.8 7185 0012 SC1425 DONE
vmepcS2F19-07 Green led ecalod-07 ecalod-S2D07d ecalfed-619 619 620 621 00 29 28 -10 -11 -12 ecalod-EBm4 A2818:0.8 7185 0007 SC1425 DONE
vmepcS2F19-08 Green led ecalod-08 ecalod-S2D08d ecalfed-622 622 623 624 14 33 32 -13 -14 -15 ecalod-EBm5 A2818:0.8 7185 0019 SC1425 DONE
vmepcS2F19-09 Green led ecalod-09 ecalod-S2D06d ecalfed-625 625 626 627 03 07 19 -16 -17 -18 ecalod-EBm6 A2818:0.8 7185 0017 SC1425 DONE
EB+
vmepcS2F19-10 Green led ecalod-10 ecalod-S2D04h ecalfed-628 628 629 630 12 17 10 +01 +02 +03 ecalod-EBp1 A2818:0.8 7185 0005 SC1425 DONE
vmepcS2F19-11 Green led ecalod-11 ecalod-S2D02h ecalfed-631 631 632 633 01 08 04 +04 +05 +06 ecalod-EBp2 A2818:0.8 7185 0020 SC1425 DONE
vmepcS2F19-12 Green led ecalod-12 ecalod-S2D03h ecalfed-634 634 635 636 27 20 23 +07 +08 +09 ecalod-EBp3 A2818:0.8 7185 0010 SC1425 DONE
vmepcS2F19-13 Green led ecalod-13 ecalod-S2D07h ecalfed-637 637 638 639 25 06 34 +10 +11 +12 ecalod-EBp4 A2818:0.8 7185 0009 SC1425 DONE
vmepcS2F19-14 Green led ecalod-14 ecalod-S2D08h ecalfed-640 640 641 642 35 15 18 +13 +14 +15 ecalod-EBp5 A2818:0.8 7185 0016 SC1425 DONE
vmepcS2F19-15 Green led ecalod-15 ecalod-S2D06h ecalfed-643 643 644 645 30 21 09 +16 +17 +18 ecalod-EBp6 A2818:0.8 7185 0013 SC1425 DONE
EE+
vmepcS2F19-16 Green led ecalod-16 ecalod-S2D06l ecalfed-646 654 646 647 D2 D2 D2 +06 +07* +08* ecalod-EEp1   todo.gif 7185 0003 SC1425 DONE
vmepcS2F19-17 Green led ecalod-17 ecalod-S2D02l ecalfed-648 648 649 650 D2 D1 D1 +09 +01 +02* ecalod-EEp2   todo.gif 7185 0004 SC1425 DONE DCCs with 8MB spy memory
vmepcS2F19-18 Green led ecalod-18 ecalod-S2D07l ecalfed-651 651 652 653 D1 D1 D1/2 +03* +04 +05 ecalod-EEp3   todo.gif 7185 0001 SC1425 DONE
SRP and Test
vmepcS2F19-19 Green led ecalod-19 ecalod-S2D05h ecalfed-661 661 662 663 664   ecalod-srp todo.gif SRP SC1425 DONE
vmepcS2F19-20 Green led ecalod-20 ecalod-S2D05e   ecalod-test and ecalod-TTCf A2818:0.8 TTCf Crate SC1425 DONE
2U Units
vmepcS2F19-21 Green led ecalod-21   ecalod-spare Hot spare VME A2818:0.8 External site 2850 DONE
vmepcS2F19-22 Green led ecalod-22   ecalod-daq01 Local DAQ 1 and Trigger Supervisor Cell 2850 DONE 4x0.5GB
vmepcS2F19-23 Green led ecalod-23   ecalod-daq02 ecalod-evb01 Local DAQ 2 - Event builder ch4 2850 DONE 4x2GB
vmepcS2F19-24 Green led ecalod-24   ecalod-daq03 ecalod-evb02 Local DAQ 3 - Event builder ch5 2850 DONE 2x2GB+4x0.5GB
vmepcS2F19-25 Green led ecalod-25     old NFS RAID5 1.1TB 2850 DONE (4x0.5GB)
TTC
vmepcS2B16-04 Green led ecalod-26   ecalod-ttc also ttc-ecal TTCci and LTC control DONE
RCMS
srv-c2d06-06 Green led ecalod-27   ecalod-rc cmsrc-ecal ECAL RCMS FM DONE
Laser
ecal-laser-room-01 Green led ecalod-28       DONE
ecal-laser-room-02 Green led ecalod-29   ecalod-laser-ctrl ECAL Laser Controller DONE
ecal-laser-room-03 Green led         DONE
ecal-laser-room-04 Green led   - 1xHDD 150GB for OS
- ((5-1)HDD x 150GB) RAID5 for /localdata
ecalod-laser-xdaq ECAL Laser Supervisor  
ecal-laser-room-07 Red led         NEW
ecal-laser-room-08 Green led         DONE
ecal-laser-room-09 Red led         NEW
Dual quad cores
srv-s2f19-26 Green led ecalod-30   ecalod-dqm01 DQM node 1 1950 DONE 8x2GB
srv-s2f19-27 Green led ecalod-31   ecalod-dqm02 DQM node 2 1950 DONE 8x2GB
srv-s2f19-28 Green led ecalod-32   ecalod-xmas Non-event Data Monitoring and compile node 1950 DONE 8x2GB
LED
vmepcs2f18-25 Green led ecalod-33   ecalod-led-ctrl cmseeled ECAL LED Controller 2950 DONE No CAEN.
Storage Unit
srv-s2f19-29 Green led ecalod-34   ecalod-disk01 also ecalod-web01 ECAL Storage Unit and Local DQM GUI R410 DONE 4x1GB

Crates

In USC55 (links to 904 test results)

Fibre S2D08 S2D07 S2D06 S2D05 S2D04 S2D03 S2D02
l              
h 7185 0016 7185 0009 7185 0013   7185 0005 7185 0010 7185 0020
d 7185 0019 7185 0007 7185 0017 Test Crate 7185 0014 7185 0012 7185 0018

By Location

LHC Crate Number Where Fantray PSU Comment
7185 0002 USC55-7l 71030 193 720000 04
7185 0001 H2 71030 121 720000 04 Slot 6 pin A12 absent
7185 0003 USC55-1h 71030 121 720000 02 Spare
xxxxxxxxx USC55-1d 71030 181 719900 26 PS Spare
7185 0004 USC55-2l 71030 123 720000 17
7185 0005 USC55-4h 71030 183 720000 22
7185 0006 USC55-6l 71030 167 720000 18
7185 0007 USC55-7d 71030 168 720000 13
7185 0008 USC55-8l 71030 169 720000 01
7185 0009 USC55-7h 71030 170 720000 06
7185 0010 USC55-3h 71030 171 720000 23
7185 0011 904 71030 172 720000 08  
7185 0012 USC55-3d 71030 173 720000 03
7185 0013 USC55-6h 71030 166 720000 11
7185 0014 USC55-4d 71030 175 720000 21
7185 0015 USC55-5f Fout 71030 190 720000 26
7185 0016 USC55-8h 71030 191 720000 09
7185 0017 USC55-6d 71030 192 720000 24
7185 0018 USC55-2d 71030 185 720000 07
7185 0019 USC55-8d 71030 194 720000 12
7185 0020 USC55-2h 71030 195 720000 05
71850021 USC55-3l 71030 184 720000 19
71850022 USC55-4l 71030 122 720000 14
SRP USC55-5l 71070157 711300 05

--- LAB20 --- 720000 25 New -Spare
--- LAB20 --- 720000 26 New- Spare

spare USC55-1 71030 174    
spare USC55-1 71030 275    
spare USC55-1 71030 276    
spare USC55-capboard   720000 15
spare USC55-capboard   719900 25
spare USC55-capboard   719900 23

TTC information

S1E03j crate module ECAL TTC partition Obs.
1 LTC  
12 EB+  
14 EB-  
15 EE+ CTC input
17 EE-  
19 ES+  
21 ES-  

LTC FMM inputs

1 2 3 4 5 6
EE- EB- EB+ EE+ ES- ES+

TTCf slot assignment in crate S2D05j

18 19 20 21
EE+ EE- EB- EB+

Topic attachments
I Attachment History Action Size Date Who Comment
Unknown file formatgz jamplayer_linux.tar.gz r1 manage 78.0 K 2006-07-13 - 21:57 AndreDavid Altera's jamplayer ported to Linux (by Tobin Fricke)
Compressed Zip archivetgz xapp058_v5.01bfad0.4.tgz r1 manage 176.2 K 2006-07-13 - 21:52 AndreDavid Xilinx's xapp058 ported to Linux and addressing a PEX8111 PCI bridge (by Tomasz Motylewski)
Edit | Attach | Watch | Print version | History: r180 < r179 < r178 < r177 < r176 | Backlinks | Raw View | WYSIWYG | More topic actions
Topic revision: r180 - 2016-03-22 - EvgueniVlassov
 
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