FNAL Prototype Pattern Recognition Mezzanine Card(protoPRM) for Pulsar2b

Device Number:




  • [ ] Before touching any boards/devices, using an anti-static wrist strap to keep your partner and yourself grounded;
  • [ ] When moving any boards/devices, using anti-static bags or boxes;

Top and back view


Visual Test

  • [ ] Before installing heat sink, checking the type of FPGA: UltraScale Kintex FPGA XCKU040 FFVA1156 -2E or XCKU060
  • [ ] Make sure all the components are soldered properly, and in correct orientation:
    • Soldering quality;
    • Orientation of IC's: a small tick and module name is around the IC. Below is an example:
    • FMC_IC.PNG
    • polarity of capacitors:13x 330uF Tantalum Capacitors
    • FMC_Polarized_Cap.PNG
    • The two fuses (2A or 4A) are installed: left bottom corner of the back side
    • FMC_Fuse.PNG
  • [ ] Measure the resistance value between each power supplies TP (Test Point) to GND TP with a multimeter. Make sure there is no shortcut between power supplies and GND;
    • Mezz2_power_dist.PNGMezz2_power_dist2.PNG
Power Rail Reference Value (ohm) Measured Value (ohm)
P0 36K(need a long time to be stable)  
P1 480  
P2 4.5  
P3 170  
P4 330  
P5 310  
P6 62  
P7 300K  

  • [ ] Measure the resistors' value. ~10% difference between the reference value and measured value is acceptable.
    • Mezz2_resistors.PNG
Resistor Value in Schematics (ohm) Reference Value (ohm) Measured Value (ohm)
R4 30.0K 21K  
R8 10.0K 8.9K  
R12 34.8K 22.8K  
R16 13.3K 11.4K  
R21 20.0K 16.0K  

Standalone Voltage Test

Dual Output Power Supply

For standalone test, two voltages are needed: 12V and 3.3V. Below is the schematic, and pin assignment for the standalone power plug/socket. (When standalone testing, could increasing 3.3V to 3.35V)


When turning on the power, the initial currents of the 12V and 3.3V output are ~0.4A.

Board Status LED Indicators


These green colored LEDs are located on the top middle of the backside.

Test Points for All Power Planes


Voltage Polarity for Tantalum Capacitors


FPGA Firmware Test


1) When developing the firmware, please define the "RSETN" pin as a input port. If not, the "RSETN" pin will be in "floating" status, which could pull down the "RESET" signal (voltage of R24), and keep the whole PRM board in "reset" status;


LED Blinking Test

There are 8(8) LEDs directly controled by the master(slave) FPGA. LEDBlinker firmware is the most basic firmware, which is like the "Hello World" codes in C/C++ language. If all these LEDs are blinking as expected, the most part of our PCB design is right.

The default system clock for the master and slave FPGAs are 100MHz. The fastest LED blinking frequence is 1.5Hz.

Blinking Firmwares for XCKU040: LEDBlinker_master.bit, LEDBlinker_slave.bit

Blinking Firmwares for XCKU060:

If you want to program the SPI Flash memory with this blinking firmware, xilinx ducoment is here: XAPP1233

After you programmed the SPI memory, when next time you turn on the mezzanine card, the firmware will be automatically loaded to the FPGA, and the LEDs start to blinking.

Bin file is here: LEDBlinker_master.bin , LEDBlinker_slave.bin;

SPI memory type is: n25q256-3.3v-spi-x1_x2_x4

IBERT Test for GTH Lines

(Please use vivado 2015.2)

PLL chosen for different Speed: QPLL0 9.816.3 GHz; QPLL1 8.013.0 GHz; CPLL <8.0 GHz

Local GTH Bus between Master FPGA and Slave FPGA

start from 6Gb/s to 16.25Gb/s; LGTH3 are special; Default reference CLK is 125MHz;

  6.25Gb/s 8.0Gb/s 10.0Gb/s 12.5Gb/s 15.625Gb/s
Master FPGA Local_Master_6p25Gbps.bit Local_Master_8Gbps.bit
Local_Master_10Gbps.bit Local_Master_12p5Gbps.bit Local_Master_15p625Gbps.bit
Slave FPGA Local_Slave_6p25Gbps.bit Local_Slave_8Gbps.bit
Local_Slave_10Gbps.bit Local_Slave_12p5Gbps.bit Local_Slave_15p625Gbps.bit
TCL script for fast setup and measure Eye-Diagrams in vivado: vivado_Mezz2_localbus_setup.tcl vivado_Mezz2_localbus_scan.tcl


Master FPGA 228 Quad and Slave FPGA 226 Quad are used for QSFP+ connection. The default reference clk is 156.25MHz.

  6.25Gb/s 10.3125Gb/s
Master FPGA QSFP_Master_6p25Gbps.bit QSFP_Master_10p3125Gbps.bit
Slave FPGA QSFP_Slave_6p25Gbps.bit QSFP_Slave_10p3125Gbps.bit
TCL script for fast setup and measure Eye-Diagrams in vivado: vivado_Mezz2_QSFP_setup.tcl vivado_Mezz2_QSFP_scan.tcl

FMC GTH lines between Pulsar2b and Master FPGA

Default reference CLK is 66.66MHz.

  8.0Gb/s 10.0Gb/s
Master FPGA FMC_Master_8Gbps.bit FMC_Master_10Gbps.bit
(These firmwares are not suggested to be used, because the reset pin is not defined)

There is a 125MHz refclk for local GTH bus could also be used by the FMC GTH:

  6.25Gb/s 8.0Gb/s 10.0Gb/s
Master FPGA FMC_Master_6p25Gbps_ref125.bit FMC_Master_8Gbps_ref125.bit FMC_Master_10Gbps_ref125.bit
Pulsar2b bit file bit file bit file
TCL script for fast setup and measure Eye-Diagrams in vivado: vivado_Mezz2_FMC_setup.tcl vivado_Mezz2_FMC_scan.tcl

Run QSFP+, LOC, and FMC GTHs at Same Time

QSFP+ and FMC GTHs is driving at 10.0 Gb/s with refclk=125MHz; LOC GTHs is driving at 15.625Gb/s with refclk=125MHz;

Be careful about the FPGA Temperature.

Master FPGA: MasterFPGA_AllGTH.bit

Slave FPGA: SlaveFPGA_AllGTH.bit


LVDS Bus is several 1Gb/s I/O lines. 1.8V

Local LVDS between Master and Slave FPGA

24 pairs LVDS

FMC LVDS between Pulsar2b and Master FPGA

22 pairs each FMC connector

I2C Interface

The Master FPGA could control the clock generator, temperature sensor, QSFP+ connectors, and voltage regulators through I2C.

Clock Generator

The default clock frequencies provied by the clock generator are:

CLOCK F(MHz) AC coupling Capacitors
Master FPGA QSFP 156.25 C56,60
Slave FPGA QSFP 156.25 C63,64
Master FPGA Local Bus 125 C65,66
Slave FPGA Local Bus 125 C67,68
Master FPGA FMC 66.66 C67,68
Master FPGA SYSCLK 100 C74,75
Slave FPGA SYSCLK 100 C71,72
The simplest way to measure the frequency is by checking the AC coupling capacitors with oscilloscope, but be careful. By this way, you don't need programming the FPGA's.

There are 2 firmwares, LEDBlinker_clock_forward_master.bit and LEDBlinker_clock_forward_slave.bit, that could forward the sysclk, QSFP+, LOC, and FMC refCLK to testpoint. The master FPGA's clocks are sent to P11, and slave FPGA's are sent to P12.

TP[0] is sysclk, TP[1] is QSFP+ clk, TP[2] is local bus clk, and TP[3] is fmc clk. (There is no fmc clk in slave FPGA)

Could use I2C interface to change the clock generator output frequency: top_changeY0Y1from156p25to125.bit and top_changeY2Y3from125to250.bit

Here is a simple I2C master VHDL code: https://www.eewiki.net/display/LOGIC/I2C+Master+(VHDL).


Static RAM is a low latence memory device.


Next generation VIPRAM Chip

-- ZijunXu - 2015-05-26

Topic attachments
I Attachment History Action Size Date Who Comment
PNGpng BottomLayer.PNG r1 manage 516.8 K 2015-05-26 - 23:47 ZijunXu  
SVG (Scalable Vector Graphics)svg ESD_Protected.svg r1 manage 2.1 K 2016-04-06 - 17:18 ZijunXu  
PNGpng FMC_Fuse.PNG r1 manage 892.3 K 2015-06-22 - 18:01 ZijunXu  
PNGpng FMC_IC.PNG r1 manage 28.8 K 2015-05-26 - 23:47 ZijunXu  
Unknown file formatbit FMC_Master_10Gbps.bit r1 manage 4298.0 K 2015-06-25 - 22:55 ZijunXu  
Unknown file formatbit FMC_Master_10Gbps_ref125.bit r2 r1 manage 4297.6 K 2015-08-16 - 18:16 ZijunXu  
Unknown file formatbit FMC_Master_6p25Gbps_ref125.bit r2 r1 manage 4050.8 K 2015-08-16 - 18:17 ZijunXu  
Unknown file formatbit FMC_Master_8Gbps.bit r1 manage 4353.8 K 2015-06-25 - 22:54 ZijunXu  
Unknown file formatbit FMC_Master_8Gbps_ref125.bit r2 r1 manage 4198.1 K 2015-08-16 - 18:18 ZijunXu  
PNGpng FMC_Polarized_Cap.PNG r1 manage 659.8 K 2015-05-26 - 23:47 ZijunXu  
PNGpng FMC_Polarized_Cap2.PNG r1 manage 1360.4 K 2015-05-28 - 17:29 ZijunXu  
Unknown file formatbit LEDBlinker_clock_forward_master.bit r1 manage 2290.2 K 2015-07-18 - 01:20 ZijunXu  
Unknown file formatbit LEDBlinker_clock_forward_slave.bit r1 manage 2296.1 K 2015-07-18 - 01:20 ZijunXu  
Unknown file formatbin LEDBlinker_master.bin r2 r1 manage 2177.6 K 2015-07-22 - 01:18 ZijunXu  
Unknown file formatbit LEDBlinker_master.bit r3 r2 r1 manage 2177.7 K 2015-07-22 - 01:19 ZijunXu  
Unknown file formatbin LEDBlinker_slave.bin r2 r1 manage 2133.4 K 2015-07-22 - 01:19 ZijunXu  
Unknown file formatbit LEDBlinker_slave.bit r3 r2 r1 manage 2133.5 K 2015-07-22 - 01:20 ZijunXu  
Unknown file formatbit Local_Master_10Gbps.bit r1 manage 4628.8 K 2015-08-24 - 17:56 ZijunXu  
Unknown file formatbit Local_Master_12p5Gbps.bit r1 manage 4725.8 K 2015-06-24 - 23:35 ZijunXu  
Unknown file formatbit Local_Master_15p625Gbps.bit r1 manage 4575.2 K 2015-06-24 - 23:36 ZijunXu  
Unknown file formatbit Local_Master_6p25Gbps.bit r1 manage 4607.2 K 2015-06-24 - 23:35 ZijunXu  
Unknown file formatbit Local_Master_8Gbps.bit r1 manage 4628.0 K 2015-07-16 - 20:21 ZijunXu  
Unknown file formatbit Local_Slave_10Gbps.bit r1 manage 4310.0 K 2015-08-24 - 17:57 ZijunXu  
Unknown file formatbit Local_Slave_12p5Gbps.bit r1 manage 4351.4 K 2015-06-24 - 23:36 ZijunXu  
Unknown file formatbit Local_Slave_15p625Gbps.bit r1 manage 4385.4 K 2015-06-24 - 23:37 ZijunXu  
Unknown file formatbit Local_Slave_6p25Gbps.bit r1 manage 4266.8 K 2015-06-24 - 23:36 ZijunXu  
Unknown file formatbit Local_Slave_8Gbps.bit r1 manage 4274.5 K 2015-07-16 - 20:21 ZijunXu  
Unknown file formatbit MasterFPGA_AllGTH.bit r1 manage 6163.5 K 2015-07-22 - 17:48 ZijunXu  
PNGpng Mezz2_power_dist.PNG r2 r1 manage 448.3 K 2015-05-28 - 17:31 ZijunXu  
PNGpng Mezz2_power_dist2.PNG r1 manage 690.6 K 2015-05-28 - 04:29 ZijunXu  
PNGpng Mezz2_powsupply.PNG r3 r2 r1 manage 235.7 K 2015-06-22 - 18:33 ZijunXu  
PNGpng Mezz2_resistors.PNG r2 r1 manage 825.9 K 2015-05-28 - 05:22 ZijunXu  
PNGpng Mezz2_sysLED.PNG r1 manage 36.8 K 2015-05-28 - 17:08 ZijunXu  
Unknown file formatbit QSFP_Master_10p3125Gbps.bit r1 manage 15631.9 K 2015-06-24 - 23:38 ZijunXu  
Unknown file formatbit QSFP_Master_6p25Gbps.bit r1 manage 15631.9 K 2015-06-24 - 23:37 ZijunXu  
Unknown file formatbit QSFP_Slave_10p3125Gbps.bit r1 manage 3820.5 K 2015-06-25 - 00:01 ZijunXu  
Unknown file formatbit QSFP_Slave_6p25Gbps.bit r1 manage 3517.5 K 2015-06-25 - 00:01 ZijunXu  
Unknown file formatbit SlaveFPGA_AllGTH.bit r2 r1 manage 4873.9 K 2015-07-22 - 21:06 ZijunXu  
PNGpng TopLayer.PNG r1 manage 409.5 K 2015-05-26 - 23:47 ZijunXu  
Unknown file formatbit top_changeY0Y1from156p25to125.bit r1 manage 2462.7 K 2015-07-21 - 18:24 ZijunXu  
Unknown file formatbit top_changeY2Y3from125to250.bit r1 manage 2508.7 K 2015-07-21 - 18:24 ZijunXu  
Unknown file formattcl vivado_Mezz2_FMC_scan.tcl r1 manage 3.3 K 2015-07-24 - 18:46 ZijunXu  
Unknown file formattcl vivado_Mezz2_FMC_setup.tcl r1 manage 25.8 K 2015-07-24 - 18:46 ZijunXu  
Unknown file formattcl vivado_Mezz2_QSFP_scan.tcl r1 manage 2.5 K 2015-07-24 - 18:46 ZijunXu  
Unknown file formattcl vivado_Mezz2_QSFP_setup.tcl r1 manage 8.0 K 2015-07-24 - 18:46 ZijunXu  
Unknown file formattcl vivado_Mezz2_localbus_scan.tcl r1 manage 4.5 K 2015-07-24 - 18:46 ZijunXu  
Unknown file formattcl vivado_Mezz2_localbus_setup.tcl r1 manage 10.3 K 2015-07-24 - 18:46 ZijunXu  
Edit | Attach | Watch | Print version | History: r40 | r33 < r32 < r31 < r30 | Backlinks | Raw View | Raw edit | More topic actions...
Topic revision: r31 - 2016-04-11 - ZijunXu
    • Cern Search Icon Cern Search
    • TWiki Search Icon TWiki Search
    • Google Search Icon Google Search

    Main All webs login

This site is powered by the TWiki collaboration platform Powered by PerlCopyright & 2008-2020 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback