-- TaoHuang - 2019-08-09

This twiki is dedicated to GEM-CSC OTMB firmware development and test at bat904

<br />

Red led --> PENDING

Yellow led --> IN PROGRESS

Green led --> DONE

Things that are not clear yet are highlighted in RED.

Linux shell commands are highlighted in YELLOW

Linux shell output is highlighted in AQUA (blue)

Verilog/C/C++ code is highlighted in LIME (green)

ME1/1 test stand operation at bat904

This section is to indicate how to operate ME1/1 test stand, including HV, LV, gas, software, and run the cosmic ray test. The standard instruction is included here: https://twiki.cern.ch/twiki/bin/viewauth/CMS/CSCB904LocalRun

HV and LV control

  • HV control: the HV control CAEN is next to ME1/1 crate and the ME1/1 chamber in test stand could be turned on through ME1/1 channel. The nominal voltage is 2894V and dark current should be close to 0
  • LV control: connect to remote desk emu-dcs-dev1.cern.ch with usrname+password = ops+******

gas control

software

before using ME1/1 test stand software, first you should tunnel to bat904 private network. The instruction is following:

how to check out and compile new Emulib software . Emulib14 is the master branch ,2019-08

notes:

  • If BC0 signal on CCB front panel is not on, then try to configure the TTCci control.
  • 2019-08-17, the DCFEB on the 3rd position is very noisy and even with HV off, it could produce pretriggers and CLCTs!

GE1/1 test stand operation (coffin) at bat904

The GE1/1 rack includes two micro-crates. The top crate is used to serve the GE2/1 and the bottom one to serve GE1/1 coffin test stand. The AMC13 provides clock, timing and DAQ service to the GEM uTCA crate either from the the TCDS system (at P5) or in local loopback mode (at a test stand). One micro-crate could serve up to 12 CTP7s and one CTP7 could serve 12 GE1/1 super chambers. In P5 commissioning, each endcap used one micro-crate to accommodate 6 CTPs for 36 GE1/1 super chambers.

Turning on the LV and HV supplies

Both the LV and HV for coffin are controlled through the CAEN PS module
  • This can be accessed from within the CERN network via telnet 128.141.143.248 1527
  • Alternatively you may control this by physically logging into the module on the rack

To login control , the user name is 1527

LV Control

Navigate to the line name coffinv3 and turn it ON. use tag to navigate back.
  • You can visually check the GEM is turned on by inspecting it's LEDs

HV Control

Connecting to RCMS (DAQ)

  1. Enter gem904daq01.cern.ch:10000/rcms in the address bar of you web browser
    • To login both username and password are: gempro
  2. Navigate to the Integration Test stand
  3. Select the uFEDKIT_TTCex configuration
Red led Question: how to setting the GEM configuration to control GE1/1 operation

Control from terminal

General instruction of GE1/1 operation: https://github.com/cms-gem-daq-project/sw_utils/blob/develop/v3ElectronicsUserGuide.md#using-gem_regpy
  1. Ask Misha to add your ssh key into lists and logon to gem904daq01 by ssh gemuser@gem904daq01NOSPAMPLEASE.cern.ch
  2. login to CTP7 control node (eagleXX). the GE1/1 coffin test stand use eagle32 by ssh gemuser@eagle34 (eagle64 is for GE2/1 test stand)

Start AMC13 and configure the system

  1. Logon to gem904daq01 and then enter AMC13 by AMC13Tool2.exe -i gem.shelf01.amc13 -c $GEM_ADDRESS_TABLE_PATH/connections.xml
  2. To reload the FW in the AMC13 enter the AMC13Tool2.exe tool and execute reconfigureFPGAs. It did nothing to downstream board
  3. To enable clock on a AMC slot, after entering AMC13, do ws CONF.TTC.OVERRIDE_MASK 0xfff and en slot_numbers, e.g. en 2 for GE1/1 test stand as CTP7 is inserted at slot2 in AMC crate, t means to enable TTC loopback mode

Load new firmware to CTP7 and configure CTP7

commonly used commands defined in gem_reg.py

  1. kw read value of reigsters including the keyword, same as readKW, like kw GEM_AMC.TRIGGER.OH0.LINK to check OH trigger link status
  2. rwc read values of registers matched to pattern with wild card, like rwc GEM_AMC.TRIGGER.OH0.LINK* to check OH trigger link status , rwc *OH0.VFAT*LINK_GOOD to check VFAT status of OH0. rwc GEM_AMC*OH0*RELEASE
  3. read read value of register and write write value to register
  4. execute full recovery by recover.sh after ssh gemuser@eagleXX

Load new firmware to OH and configure OH

OH firmare is automatically loaded from CTP7 by every hardreset.
  1. To load the new OH firmware, firstly copy the bit file to /mnt/persistent/gemdaq/oh_fw/ by scp optohybrid_top_BC0.bit root@eagle34:/mnt/persistent/gemdaq/oh_fw/. Get root password from Misha etc.
  2. Login to the CTP7 and create a symlink to the new FW bit file with the name optohybrid_top.bit. ln -sf optohybrid_top_BC0.bit optohybrid_top.bit
  3. source /mnt/persistent/gemdaq/gemloader/gemloader_configure.sh
  4. issue hard reset , either from CTP7, AMC13 or TTC . generate hardreset from CTP7 by write GEM_AMC.TTC.GENERATOR.SINGLE_HARD_RESET 1 and write GEM_AMC.TTC.GENERATOR.ENABLE 1 is to enable TTC command in CTP7.
  5. in case of power-cycle, reset the slow control by write GEM_AMC.SLOW_CONTROL.SCA.CTRL.MODULE_RESET 1 and check SCA status by rwc GEM_AMC.SLOW_CONTROL.SCA*STATUS* . Resetting SCA is to bring back the communication to OH.

Reset GBT

  1. reset GBT link by write GEM_AMC.GEM_SYSTEM.CTRL.LINK_RESET 0x1 , and check OH0's GBT status by kw OH_LINKS.OH0.GBT
  2. Program GBT by gbt.py Y X config for GBT X for OH Y. configuration file is under /mnt/persistent/gemdaq/gbt/OHv3c on eagle34 for GE1/1 test stand

Collecting Data and Analysis

Red led how to take the cosmic ray data with GE1/1 test stand and how to analyze the data

GEM-CSC OTMB Firmware test in 2019August

GEM-CSC OTMB firmware features

  1. Receive GEM fibers and synchronize the GEM fibers with CSC fibers by adjusting the phase and integer BX delay
  2. Unpack GEM cluster from GEM fibers and build GEM copads from GEM clusters
  3. Counters to record status of GEM cluster, sync, copads, VFATs
  4. Synchronize GEMs with CLCT using BC0 and BC0 timing scan
  5. Match GEM cluster with ALCT(CSC anode trigger) and CLCT(CSC cathode trigger) in timing
  6. Read out GEM cluster in OTMB DAQ path

Sequence of changing AMC from loopback mode to TTC clock

  1. Remove loopback fiber and plug in TTC clock fiber
  2. Reprogram AMC13 by AMC13Tool2.exe -i gem.shelf01.amc13 -c $GEM_ADDRESS_TABLE_PATH/connections.xml, then reconfigureFPGAs, enable TTC clock for CTP7(at slot2) ws CONF.TTC.OVERRIDE_MASK 0xfff and en 2
  3. On eagle34, cold boot CTP7. Go to /mnt/persistent/gemdaq/scripts/ and do ./cold_boot_invert_tx.sh
  4. Execute gemloader_configure.sh under /mnt/persistent/gemdaq/gemloader
  5. Configure GBTX by gbt.py Y X config config_file for GBT X of OH Y. GBT configuration file is under /mnt/persistent/gemdaq/gbt/OHv3c. you could check GBT status by kw OH_LINKS.OH0.GBT after entering gem register interface
  6. Before loading OH fw with hardreset, ssh root@eagle34, go /mnt/persistent/gemdaq/oh_fw and change the symlink of OH fw bit
  7. gem_reg.py and connect eagle34 to enter gem register interface
  8. Check the slow control SCA status by kw GEM_AMC.SLOW_CONTROL.SCA.STATUS. Make sure you see no critical err, otherwise do a trigger module reset by write GEM_AMC.SLOW_CONTROL.SCA.CTRL.MODULE_RESET 1
  9. write GEM_AMC.TTC.CONFIG.CMD_BC0 0x4 and write GEM_AMC.TTC.CONFIG.CMD_RESYNC 0xc to make sure CTP7 could correctly decode TTC command
  10. Disabled TTC command generator to allow CTP7 to TTC command from TTC clock by write GEM_AMC.TTC.GENERATOR.ENABLE 0, or Enable TTC command generator and do hardreset from TTC. TTC generator should be disabled during test.
  11. Reset trigger link after each hardreset write GEM_AMC.GEM_SYSTEM.CTRL.LINK_RESET 1
  12. Finally check OH firmware release and link status by kw GEM_AMC.OH.OH0.FPGA.CONTROL.RELEASE, kw GEM_AMC.TRIGGER.OH0

LTC and TTC control

  1. Create local.duck and configure LTC and TTC by navigating to each control page
  2. Check last TTC command is BC0 on CCB status, or check the BC0 led on CCB front panel. If BC0 is not available, usually resetting TTC could bring it back
  3. Could issue hardrest/resync etc TTC command from LTC control page
  4. Could also enable periodic resync from LTC control page. make sure that you click startPermanent to enable it permanently

GEM related OTMB registers

GEM-CSC joint run

  • Connect the CSC fiber from Opto-hybrid board to CSC OTMB fiber
  • Switch from CTP7 internal clock to TTC clock for GE1/1
  • In OTMB configuration(xml file), enable GEM inputs. after crate is on and power-up init is done, do write-flash
    • GEM configuration parameters: gem_enabled="1" gem_read_enable="1" decouple_gem_rxd_int_delay="0" gem_fifo_rxd_int_delay="8" gem_delay="18" gem_posneg="0" gem_decouple="1" gem_fifo_tbins="16"
    • 2018OTMB configuration parameters: use_dead_time_zone="1" dead_time_zone_size="15" use_dynamic_dead_time_zone="1" drop_used_clcts="0" cross_bx_algorithm="1" clct_to_alct="0" clct_match_window_size="3"
  • Synchronize GEM fibers and CSC fibers
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Topic revision: r14 - 2019-09-19 - TaoHuang
 
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