Hcal TP Rate Monitoring

General information about the HTR board (search the "DATA FORMATS" link for more details of the HTR data formats and internal logic).

Rate Monitoring in the HTR

Major resource requirements

To provide HCAL TP Rate Monitoring, the following is necessary:

  • Two scalars of at least 24 bits (32 preferable) per TP channel
  • Independent (8-bit) thresholds for each scalar for each channel (up to 48 thresholds/FPGA)
  • For each TP channel, the first scalar counts the number of times the channel sends a value between the lower threshold and the upper threshold to the SLB. The second scalar counts the number of times the channel sends a value at-or-above the upper threshold.
  • Common control of enable/clear for all scalars
  • Normalization scalar which indicates the number of bunches for which the scalars were active [one per FPGA]

Scalar control logic

  • Clear bit which clears all scalars (one-shot if possible)
  • Enable bit which enables all scalars including the normalization scalar
  • Scalars are stopped by either enable bit being cleared or normalization scalar reaching (2**24 - 1) [ or 2**32-1 if larger scalars are used ]

-- JeremyMans - 01 Aug 2008

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Topic revision: r4 - 2010-02-03 - TullioGrassi
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