Hcal TP Rate Monitoring

General information about the HTR board

Technical Triggers in HCAL

Using the HCAL detector data, the HTR and in the TTP boards generate three technical triggers (sent to GT):

  • HBHE (pure HB excluded)
  • HO
  • HF
  • ZDC (to-be done)

Algorithm in HBHE and HO

The HBHE and HO technical triggers are generated with the following steps (for every LHC bunch):

1) a single HTR FPGA does receive 24 digitized detector channels (= QIE channels) and linearize them (via the Input-LUTs).

2) each detector channel (if valid this represents an energy sample) is compared to a programmable threshold (named TechTrigHitThreshold in the HAL table and in the CfgScripts). A bit is asserted if the energy sample is above the TechTrigHitThreshold and if the energy sample is a local maximum (=peak).

3) A logical-OR operation is performed in a HTR FPGA on the 24 bits resulting from the step 2) above. The result is a bit (sometimes called TotalOR).

4) Each HTR FPGA sends the TotalOR bit to the TTP board.

5) The TTP board generates a technical trigger based if the number of TotalOR bits that it received is above a certain threshold.

NB: the same FPGA can generate and transmit a second bit, whose behavior is not specified and can be for test purposes.

Algorithm in HF

The HF technical trigger generation is different in the step 1) and 2) :

1) the channel is linearized and the transverse-energy (Et) is calculated.

2) a bit is asserted if the Et sample is above the TechTrigHitThreshold without requiring it to be a local maximum.

Steps 3-5 are the same as HBHE.

-- TullioGrassi - 07-Jan-2010

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Topic revision: r4 - 2010-03-03 - TullioGrassi
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