ICEPP SLr Upgrade hardware work


This page for LAr hardware work for Phase-1 and Phase-2 upgrade project. Short term target is establish a LAr readout system at a testbench in the EMF. Long term target is establish backend electronics for Phase-2!!

Now we are working on building a testbench of LAr readout system.

Here is list of Idea for future tasks. IceppLArHardTasklist.

LAr readout testbench

(Text here will be updated....) Detector --> FrontEnd electronics --> USA15 (Backend electronics), receiving analog signal. LAr electronics in backend --> DAQ |--> Trigger Receiver --> L1CAL

Now LAr group doesn't have a setup to read Trigger Receiver output. In Phase-1 upgrade, Trigger Receiver will be updated, and will have enough buffer to check this output. In order to test new board, we need to have test framewark including Trigger receiver readout.

Short term project for ICEPP is to establish full readout DAQ system in the EMF. Basically we need to take care of VME readout system. We will work with Luis Hervas (CERN).

Trigger Reciver test bench

Trigger Receiver test bench is located in B3150, room 13. There is a crate crate trigger receiver boards (TRB), and a crate for VME to control TRB crate and readout frash ADC module in VME crate. First task is to read a frash ADC in a VME crate.

In order to access VME crate

One needs to have proper Point1 access role, because the setups are in Point1 network. After making proper contact with Luis Hervas (, Go to, and register LAR:DAQ:expert, CAL:DAQ:expert, and LAR:Remote. This registration works in two step, one request "Assignment" as the first step, and then "Enabling" as the second step.

Once you have proper roles, you can login console in any Point1 network. The VME controler is sbc-lar-mon-emf-01 which is side of the VME crate. From remote, you can access the VME crate by following steps:

  1. ssh
  2. ask for access, provide justification, like "in order to access LAr testbench in bld 3150 for testing trigger receiver board.".
  3. You will be granted by Shift leader, you can login to "pc-lar-scr-mon-02" (need to type host name).
  4. Once you are in pc-lar-scr-mon-02, you can ssh to sbc-lar-mon-emf-01.

Note: Sometimes, the shift leader wants to know the details, why you need to have remote access, where you log in, who authorized etc.. You may need to call the shift leader (71388). Just in case, you should know the phone number of LAr Run Coordinator (70136) in case you make changes on the LAr detector online readout.

Some details of VME crate control

Current Yuji's working environment:

  • /atlas-home/0/yenari/test/mycode/example/
  • /atlas-home/0/yenari/test/mycode/vme_universe --> this works.
  • source /atlas-home/0/yenari/test/mycode/
  • gcc -I /atlas-home/0/yenari/test/vme_universe/include/ -g -DDEBUG peek.c -Lvme -L /atlas-home/0/yenari/test/vme_universe/lib -lvme -o peek
  • The serial number of ADC module can be read with "peek".
  • Now checking myadc.c in /atlas-home/0/yenari/test/mycode/example/, with Makefile.

Test bench status and outputs

Simulation studies

R&D board with FPGA and MicroPOD

  • DDR3
    • MT41J128M16HA-187E:D
      • 2GB = 128MB x 16
      • DDR3-1066
      • 1.87ns (CL=7)
        • 1.785ns - 2.590ns -> 500MHz is good enough?


  • Yuji Enari x78835, b188-5-002
  • Junichi Tanaka x74245, b188-5-004
  • Shimpei Yamamoto x74902, b188-5-004
  • Luis Hervas x71216, 163805 (Potable), b40-1-D01
  • Michel 165101 (Potable)

-- YujiEnari - 24-Oct-2012

Topic attachments
I Attachment History Action Size Date Who Comment
Unknown file formatpptx 20130215.pptx r1 manage 948.6 K 2013-02-25 - 10:04 YujiEnari test bench status 2013.2.15
PDFpdf 500-007750-000-Rev-G.pdf r1 manage 1172.5 K 2012-10-24 - 17:48 YujiEnari Product Manual for VME controller, VMIVME-7750.
PDFpdf FirstDoc_TriggerReceiverVMEcrate.pdf r1 manage 137.5 K 2012-10-24 - 17:45 YujiEnari A reference from Luis, describes testbench setup briefly.
PDFpdf Joerger_ADC_VTR10014_Manual.pdf r1 manage 565.7 K 2012-10-24 - 17:46 YujiEnari Manual of Frash ADC, Joerger VTR10014 (scanned version)
PDFpdf TestBench20130215.pdf r1 manage 770.0 K 2013-02-25 - 10:05 YujiEnari pdf file
PDFpdf joerger10014manA.pdf r1 manage 383.5 K 2012-10-24 - 17:47 YujiEnari Manual of Frash ADC, Joerger VTR10014, non-scanned version from SLAC.
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Topic revision: r10 - 2013-10-04 - JunichiTanaka
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