-- DarioSoldi - 2020-09-11

LiteDTU v1.0:

Documents:

Cometti's thesis: https://iris.polito.it/handle/11583/2842515#.X1twffexUUE

Working boards:

  • First production: #2 (but not receives external clock), #5 (fully functional)
  • Second production: #7 (but not receives external clock, to be re-check)
Firmware Location

Analysis Code in ADC Test MODE

The analysis code of the ADC-Test mode decodes the .txt files saved with LabView. In Labview we set 65536 samples. Each samples contains 4 words for a total of 262144 words for each channel.

It is part of root routine:

.x init.cpp

allows to load the needed functions:

  • readeth: extracts data for each channel
  • txtToRoot: saves the output in a root format
  • fit: performs the fit with a sinewave to compute the ENOB from the residuals
  • fft: extracts the ENOB from the FFT
  • fftaverage: extract the ENOB from the average of 16 different subsamples.
  • doallstep allows to performs all the above steps in a single command, but the saving format must be: date_conditions_frequency_ADC%channelID_clk%TypeOfClock.txt. example: 2020_09_20_normal_50_009765620_ADCH_extCLK.txt. The program extracts the infos from the name and performs the analysis.
Data

Results

Setup Instructions v1.0

Clock splitter:

  • V: 3.3 Volt

Turn on the clk @160MHz, connected to the clock splitter. The output of the splitter goes to the Xilinx FPGA and to the Oscilloscope.

Turn on the board: three channels have been used for the analog (3 V), digital (3 V), and drivers (4 V) power supplies. When the board is on, the currents are: analog (0.026 A), digital (0.145 A), drivers (0.134 A).

ADC TEST MODE:

  1. Send Reset sequence: Start, DTU_reset, I2C_interface_reset, AdcTestUnit_reset, ADCH_reset, ADC_L reset
  2. Write registers to turn on the components (ADCs, PLL...)
  3. Redo the above steps until the PLL is not locked (see the scope)
  4. Align the phases to have the trailing and the leading words at the beginning and at the end of the sample.
  5. Calibrate the ADCs: Input in DC: 850-350 mV to the calibration input (850 mV to the SMA connectors in J1 and J4 and 350 mV to J3 and J6).Then acquire data with calib on: ADC values must be centered to 3755 ADC counts.
  6. Turn on the RodeSwartz pulser: Coherent Frequencies: 50.009765620 MHz, or 0.498046870 MHz if the input clock is 160MHz. The input is passed into bandpass filters and goes to the input with the baloon: RodeSwartz has only 1 output.
  7. Acquire data to analyzte them.
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Topic revision: r1 - 2020-09-11 - DarioSoldi
 
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