User's guide of the ChipScope for Pixel calibration

Xilinx ChipScope


The ChipScope provides features and capabilities specific to the exploration and debug of designs that use the high-speed serial transceiver I/O capability (e.g. JTAG, XVC) of FPGAs(link).
The main debugging capability is the Integrated Logic Analyzer (ILA), which allows us to spy signals located in FPGAs in the same way as using a logic analyzer. This document describes mainly how to master ILA unit implemented on the Ly1/Ly2 Fw.

Implementation ILA units in firmwares

You can implement ILA units in firmware on two ways.
The one is to assign signals to ILA units by using a GUI tool, the another one is to write manually ILA units and connection between signals and the units in the codes of firmware.

1. Generate ILA units and CDC files from a GUI

2. Put ILA units manually in codes of the Fw

When you do not use the GUI, you have to put ILA & ICON units on codes of the Fw manually.

An ILA unit is written like...

component ILA is
  port (
    CONTROL : inout std_logic_vector(35 downto 0);
    CLK  : in  std_logic;
    TRIG0 : in  std_logic_vector(* downto 0);
    TRIG1 : in  std_logic_vector(* downto 0);
end component;

and an ICON unit is like

component ICON is
  port (
    CONTROL0 : inout std_logic_vector(35 downto 0);
    CONTROL1 : inout std_logic_vector(35 downto 0);
end component;

The ICON unit interfaces ILA units with JTAG or XVC(Xilinx Virtual Cable).

Finally, you have to connect ILA units to the ICON unit via "CONTROL" signal.

ChipScope for the Pixel calibration

CDC files

CDC(ChipScope Definition and Connection) files contain information about definition of ILA unit and connections between signals and ILA unit. The CDC files used for the Pixel calibration are named as “testOfficial_ForCalibration_ForHalfSlave[1,2].cdc” usually.

In the past, there was only one cdc file named as “testOfficial_ForCalibration.cdc”. However, now there are two CDC files depending on which half slave is used, because we had to separate it into these two CDC files in order to satisfy limitation on FPGA resource.

Connection to the ChipScope

If you are on PIT machines,
$ source /atlas/software/xilinx/14.7/ISE_DS/
$ analyzer

If you are on SR1 machines,

$ ssh -Y -l [username] [hostname connected to JTAG or XVC]
$ source daq/scripts/atlaspixeldaqrc
$ setup_xilinx
$ analyzer
$ ~karolos/scripts/run_xilinx analyzer

  • Connect to JTAG or XVC
If you are using JTAG,

[JTAG Chain] -> [Xilinx Platform USB Cable] -> [Platform USB Cable Parameters](Port:{choose S/N of the cable} , Speed:3MHz) -> [OK]

If you are using XVC,

[JTAG Chain] -> [Open Plug-in] -> [Plug-in Parameters] (xilinx_xvc HOST={MASTER_IP}:2542  disableversioncheck=true) -> [OK]

  • Open CDC files(*.cdc)
[File] -> [Import] -> [Select New File] -> (Select testOfficial_ForCalibration_ForHalfSlave[1,2].cdc) -> [Unit/Device](“DEVICE:2” for the north, “DEVICE:5” for the south) -> [OK]

  • Confirm the connection
To be written

Visible signals

Histogrammer (on ILA0)

Name Bits Summary
roc{0,1} [0]  
hitEnable{0,1} [0]  
row{0,1}Pix [7:0]  
col{0,1}Pix [4:0]  
totVal{0,1}Pix [4:0]  
chip{0,1}Pix [6:0]  
busy_hitpipe [0]  
ramAddr [18:0]  
ramdataWe_r [31:0]  
ramdataIn [31:0]  
histo{0,1} [31:0]  

Formatter (on ILA1)

Name Bits Summary
roc{0,1} [0]  
hitEnable{0,1} [0]  
row{0,1}Pix [7:0]  
col{0,1}Pix [4:0]  

Router (on ILA1)

Name Bits Summary
roc{0,1} [0]  
hitEnable{0,1} [0]  
histo{0,1} [31:0]  

Examples of trigger setting


Schematic of the Ly1/Ly2 ROD slave firmware

A ROD has two Slave FPGAs. One slave has four data paths from the BOC and these paths are divided into two identical sections called half_slave1 and half_slave2 respectively. And then a half slave has two formatter, one EFB (Event Fragment Builder) and one router.

-- KazukiYajima - 2017-05-08

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Topic revision: r2 - 2017-05-08 - KazukiYajima
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