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User's guide of the ChipScope for Pixel calibration

Xilinx ChipScope

Overview

The ChipScope provides features and capabilities specific to the exploration and debug of designs that use the high-speed serial transceiver I/O capability (e.g. JTAG, XVC) of FPGAs(link).
The main debugging capability is the Integrated Logic Analyzer (ILA), which allows us to spy signals located in FPGAs in the same way as using a logic analyzer. This document describes mainly how to master ILA unit implemented on the Ly1/Ly2 Fw.

Implementation ILA units in firmwares

You can implement ILA units in firmware on two ways.
The one is to assign signals to ILA units by using a GUI tool, the another one is to write manually ILA units and connection between signals and the units in the codes of firmware.

1. Generate ILA units and CDC files from a GUI

2. Put ILA units manually in codes of the Fw

When you do not use the GUI, you have to put ILA & ICON units on codes of the Fw manually.

An ILA unit is written like...

component ILA is
  port (
    CONTROL : inout std_logic_vector(35 downto 0);
    CLK  : in  std_logic;
    TRIG0 : in  std_logic_vector(* downto 0);
    TRIG1 : in  std_logic_vector(* downto 0);
    ...
  );
end component;

and an ICON unit is like

component ICON is
  port (
    CONTROL0 : inout std_logic_vector(35 downto 0);
    CONTROL1 : inout std_logic_vector(35 downto 0);
    ...
  );
end component;

The ICON unit interfaces ILA units with JTAG or XVC(Xilinx Virtual Cable).

Finally, you have to connect ILA units to the ICON unit via "CONTROL" signal.

ChipScope for the Pixel calibration

CDC(ChipScope Definition and Connection) files contain information about definition of ILA unit and connections between signals and ILA unit. The CDC files used for the Pixel calibration are named as “testOfficial_ForCalibration_ForHalfSlave[1,2].cdc” usually.

In the past, there was only one cdc file named as “testOfficial_ForCalibration.cdc”. However, now there are two CDC files depending on which half slave is used, because we had to separate it into these two CDC files in order to satisfy limitation on FPGA resource.

CDC files

Connection to the ChipScope

Visible signals

Examples of trigger setting

Appendix

-- KazukiYajima - 2017-05-08

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Topic revision: r1 - 2017-05-08 - KazukiYajima
 
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