User's guide of the ChipScope for Pixel calibration

Xilinx ChipScope

Overview

The ChipScope provides features and capabilities specific to the exploration and debug of designs that use the high-speed serial transceiver I/O capability (e.g. JTAG, XVC) of FPGAs(link).
The main debugging capability is the Integrated Logic Analyzer (ILA), which allows us to spy signals located in FPGAs in the same way as using a logic analyzer. This document describes mainly how to master ILA unit implemented on the Ly1/Ly2 Fw.

Implementation ILA units in firmwares

You can implement ILA units in firmware on two ways.
The one is to assign signals to ILA units by using a GUI tool, the another one is to write manually ILA units and connection between signals and the units in the codes of firmware.

1. Generate ILA units and CDC files from a GUI

  • Open ISE GUI
  • Open the project
  • Click the CDC file associated to the project or add a new CDC
  • Pick signals up as you want to spy

2. Put ILA units manually in codes of the Fw

When you do not use the GUI, you have to put ILA & ICON units on codes of the Fw manually.

An ILA unit is written like...

component ILA is
  port (
    CONTROL : inout std_logic_vector(35 downto 0);
    CLK  : in  std_logic;
    TRIG0 : in  std_logic_vector(* downto 0);
    TRIG1 : in  std_logic_vector(* downto 0);
    ...
  );
end component;

and an ICON unit is like

component ICON is
  port (
    CONTROL0 : inout std_logic_vector(35 downto 0);
    CONTROL1 : inout std_logic_vector(35 downto 0);
    ...
  );
end component;

The ICON unit interfaces ILA units with JTAG or XVC(Xilinx Virtual Cable).

Finally, you have to connect ILA units to the ICON unit via "CONTROL" signal.

ChipScope for the Pixel calibration

CDC files

CDC(ChipScope Definition and Connection) files contain information about definition of ILA unit and connections between signals and ILA unit.

The CDC files used for the Pixel calibration are named as “testOfficial_ForCalibration_ForHalfSlave[1,2].cdc” usually.

These CDC file and corresponding Fw are in...

  • PIT
    • ~kyajima/testFw/testOfficial_ForHalfSlave[1,2].cdc
    • /det/pix/daq/binaries/IBLROD/current/testFw/testOfficial_ForHalfSlave[1,2].ace
  • SR1
    • ~kyajima/testFw/testOfficial_ForHalfSlave[1,2].cdc

In the past, there was only one cdc file named as “testOfficial_ForCalibration.cdc”. However, now there are two CDC files depending on which half slave is used, because we had to separate it into these two CDC files in order to satisfy limitation on FPGA resource.

Compilation the slave Fw with the CDC file

Connection to the ChipScope

If you are on PIT machines,
$ source /atlas/software/xilinx/14.7/ISE_DS/settings64.sh
$ analyzer

If you are on SR1 machines,

$ ssh -Y -l [username] [hostname connected to JTAG or XVC]
$ source daq/scripts/atlaspixeldaqrc
$ setup_xilinx
$ analyzer
or
$ ~karolos/scripts/run_xilinx analyzer

  • Connect to JTAG or XVC
If you are using JTAG,

[JTAG Chain] -> [Xilinx Platform USB Cable] -> [Platform USB Cable Parameters](Port:{choose S/N of the cable} , Speed:3MHz) -> [OK]

If you are using XVC,

[JTAG Chain] -> [Open Plug-in] -> [Plug-in Parameters] (xilinx_xvc HOST={MASTER_IP}:2542  disableversioncheck=true) -> [OK]

  • Open CDC files(*.cdc)
[File] -> [Import] -> [Select New File] -> (Select testOfficial_ForCalibration_ForHalfSlave[1,2].cdc) -> [Unit/Device](“DEVICE:2” for the north, “DEVICE:5” for the south) -> [OK]

  • Confirm the connection
To be written

Visible signals

In signal name, braces means {<For HalfSlave1>,<For HalfSlave2>}.

I/O of Histogrammer (on ILA0)

Name Bits Summary
roc{0,1} [0]  
hitEnable{0,1} [0] Valid signal for hit data
row{0,1}Pix [7:0] Row index inputs to AddrConverter
col{0,1}Pix [4:0] Column index inputs to AddrConverter
totVal{0,1}Pix [4:0] ToT value inputs to AddrConverter
chip{0,1}Pix [6:0] Chip index inputs to AddrConverter
busy_hitpipe [0]  
ramAddr [18:0] Address inputs to the SSRAM
pipes_0 [31:0] Equals to "ramDataOut", Data outputs from the SSRAM
ramDataIn [31:0] Data inputs to the SSRAM
histo{0,1} [31:0] Data output from histogrammer to FitServer

Inputs to Formatter (on ILA1)

Name Bits Summary
rx_rod_addr_a_i [1:0] Denotes signal speed {'00'=40, '01'=2x40, '10'=80, '11'=2x80 [Mb/s]} (NOT address)
rx_rod_ctrl_a_i [0]  
rx_rod_we_b_i [0] Write enable to formatter
rx_rod_data_{a,c}_i [7:0] Data from Pixel Modules
rx_rod_data_{b,d}_i [7:0] (Usually one-to-one between modules and lines)

Outputs from Router (on ILA1)

Name Bits SummarySorted ascending
out_data_to_router [31:0] Data inputs to the router
data_valid_out [31:0] Valid signal for out_data_to_router

Trigger setting

  • Waveform will be captured by "trigger".
    • You can trigger immediately by pressing [T!] button on the top of ChipScope GUI.
    • And you can trigger at certain signal patterns set on trigger setup by pressing ▶️ button.

In "Project" sub-window, you can see a list of devices, ILA units, and etc.., and an ILA unit has 4 items(Trigger Setup, Waveform, Listing, BusPlot). To open trigger setup window, click Trigger Setup.

  • Trigger setup
    • Match Unit - A unit to set signal patterns for triggering
      • Function
        • '==' - trigger when signals equal to the pattern set on "Value"
        • '<>' - trigger when signals differ from the pattern set on "Value"
      • Value
        • 'X' - Don't care
        • '1','0' - High, Low
        • 'R','F' - Rising, Falling
        • 'B','N' - Either transition, No transition
      • Radix - Set a format for "Value" cell
      • Counter -
    • Trigger condition - Logical combination of match units
      • Trigger Condition Equation
        • Boolean - You can combine match units with AND or OR logic
        • Sequencer - You can combine match units as the certain sequence
    • Capture Setting - Setting for waveform
      • Type
        • Window -
        • N Samples -
      • Windows - The number of waveforms displayed in a "Waveform" window
      • Depth - Width of each waveforms
      • Position - An offset of trigger point from the beginning of waveform
      • Storage Qualification - ??

Examples of trigger setting

1. Any hit data
  • Input to Histogrammer
    • hitEnable == '1'
    • Don't care any other signals (== 'X')
  • Output from Router
    • data_valid_out == '1'
    • out_data_to_routor[31:29] == "100" - See Data format
    • Don't care any other signals (== 'X')
  • Input from formatter
    • Unfortunately, it is pretty hard to trigger because...
      • There are no valid signals
      • The inputs of formatter is serial.
    • Instead of hit data, you can trigger at any data(including header, trailer, error...)
      • rx_rod_data_{a,b,c,d} <>(differ from) "000..."

2. Specific hit data
  • Input to Histogrammer
    • hitEnable == '1'
    • Set values on ToT, row, column, or chipID as you want. For example...
      • Trigger at hit the column and row of which is 0 and 0--16 (Useful to reduce the number of trigger)
        • col0Pix == "00000", row0Pix == "0000XXXX"
      • Trigger at hit the chip of which is FrontEnd3
        • chip0Pix == ""
  • Output from Router
    • data_valid_out == '1'
    • out_data_to_router[31:29] == "100"
    • Set values on ToT, row, column, or FrontEnd ID as you want.
      • In the case of hit, out_data_to_router[31:0] = "100xFFFFTTTTTTTTxxxCCCCCRRRRRRRR"
    • More details, see Data format

3. Error words
Outputs from Router sometimes contain error words that are very useful for debugging of the Fw. To trigger at error words, you have to set...
  • data_valid_out == '1'
  • out_data_to_router[31:29] == "000"
  • For Type 1 error
    • out_data_to_router[28] == '0'
    • out_data_to_router[12:8] == "11110"
  • For Type 2 error
    • out_data_to_router[28] == '1'
    • out_data_to_router[20:13] == "11111000"
  • More details, see Data format

Appendix

Schematic of the Ly1/Ly2 ROD slave firmware

A ROD has two Slave FPGAs. One slave has four data paths from the BOC and these paths are divided into two identical sections called half_slave1 and half_slave2 respectively. And then a half slave has two formatter, one EFB (Event Fragment Builder) and one router.
RODBOC_DataPath.png

Data format #DataFormat

DataFormatPix.png

Reference

ChipScope Pro and the Serial I/O Toolkit WebPage

ChipScope Pro Software and Cores (v14.3)

-- KazukiYajima - 2017-05-08

Topic attachments
I Attachment History Action Size Date Who Comment
PNGpng DataFormatPix.png r1 manage 765.5 K 2017-05-09 - 12:01 KazukiYajima  
PNGpng RODBOC_DataPath.png r1 manage 335.5 K 2017-05-09 - 12:00 KazukiYajima  
Edit | Attach | Watch | Print version | History: r5 < r4 < r3 < r2 < r1 | Backlinks | Raw View | WYSIWYG | More topic actions
Topic revision: r5 - 2017-05-10 - KazukiYajima
 
    • Cern Search Icon Cern Search
    • TWiki Search Icon TWiki Search
    • Google Search Icon Google Search

    Main All webs login

This site is powered by the TWiki collaboration platform Powered by PerlCopyright &© 2008-2019 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback