Power Rails | Referece Value(Ω) | Observed Value(Ω)![]() |
---|---|---|
P1 VCC12 | 3.5K | |
P2 VCC3V3 | 3.0K | |
P3 VCC1V0 | 14.2 | |
P4 MGTAVCC 1.0V | 111 | |
P5 MGTAVTT 1.2V | 2.5K or 350 | |
P6 VCC1V8 | 650 | |
P7 MGTAVCCAUX 1.8V | 6.5K | |
P8 VCC1V5 | 511 |
Regulator | Resistor | Schematic Value (Ω) | Reference Value(Ω) | Observed Value(Ω) |
---|---|---|---|---|
U16 | R22 | 240 | 242 | |
R26 | 4.2k | 4.19k | ||
R28 | 10k | 10.05k | ||
R29 | 36.5k | 36.2k | ||
U17 | R23 | 240 | 242 | |
R27 | 30.0k | 19.7k | ||
R30 | 23.7k | 23.5k | ||
R31 | 23.7k | 23.4k | ||
U18 | R24 | 240 | 242 | |
R25 | 10k | 8.88k | ||
R32 | 23.7k | 23.5k | ||
R33 | 36.5k | 36.4k | ||
U21 | R34 | 240 | 242 | |
R36 | 30.0k | 19.6k | ||
R38 | 36.5k | 36.2k | ||
R39 | 23.7k | 23.5k | ||
U23 | R35 | 240 | 242 | |
R37 | 20.0k | 15.8k | ||
R40 | 10k | 10.05k | ||
R41 | 23.7k | 23.5k |
Initial configuration for the first testing:
At first, testing the management voltage:
Power Rails | Observed Voltage(V) |
---|---|
P1 VCC12 | |
P2 VCC3V3 | |
P3 VCC1V0 | |
P4 MGTAVCC 1.0V | |
P5 MGTAVTT 1.2V | |
P6 VCC1V8 | |
P7 MGTAVCCAUX 1.8V | |
P8 VCC1V5 | |
RTM (12V) |
RefClk 0 | MGTREFCLK0_118 |
RefClk 1 | MGTREFCLK0_115 |
RefClk 2 | MGTREFCLK0_219 |
RefClk 3 | MGTREFCLK0_112 |
RefClk 4 | MGTREFCLK0_110 |
RefClk 5 | MGTREFCLK0_211 |
RefClk 6 | MGTREFCLK0_214 |
RefClk 7 | MGTREFCLK0_217 |
GTH | Ref Clk |
210 | MGTREFCLK0_211 |
211 | MGTREFCLK0_211 |
212 | MGTREFCLK0_211 |
213 | MGTREFCLK0_214 |
214 | MGTREFCLK0_214 |
215 | MGTREFCLK0_214 |
216 | MGTREFCLK0_217 |
217 | MGTREFCLK0_217 |
218 | MGTREFCLK0_217, 219 |
219 | MGTREFCLK0_219 |
110 | MGTREFCLK0_110 |
111 | MGTREFCLK0_110, 112 |
112 | MGTREFCLK0_112 |
113 | MGTREFCLK0_112 |
114 | MGTREFCLK0_115 |
115 | MGTREFCLK0_115 |
116 | MGTREFCLK0_115 |
117 | MGTREFCLK0_118 |
118 | MGTREFCLK0_118 |
119 | MGTREFCLK0_118 |
GTH | TX | RX |
GTX211_2 (RTM) | R | - |
GTX212_2 (RTM) | - | R |
GTX212_3 (RTM) | R | - |
GTX214_0 (RTM) | - | R |
GTX218_3 (FMC) | R | - |
GTX219_1 (FMC) | - | R |
GTX219_2 (FMC) | - | R |
GTX219_3 (FMC) | R | R |
GTX110_0 (RTM) | R | R |
GTX110_1 (RTM) | R | R |
GTX110_2 (RTM) | R | R |
GTX110_3 (RTM) | R | R |
GTX111_0 (RTM) | R | - |
GTX111_2 (fab) | R | - |
GTX114_3 (fab) | - | R |
GTX118_2 (FMC) | - | R |
GTX119_1 (FMC) | R | R |
GTX119_2 (FMC) | R | - |
GTX119_3 (FMC) | - | R |
IBERT firmwares with GTH refrence CLK=200MHz | ||||||||
---|---|---|---|---|---|---|---|---|
Pulsar | Vidado (Y/N) | # of channels | Channels | Usage | Speed (Gbps) | Speed (Gbps) | Speed (Gbps) | Speed (Gbps) |
IIb | Y | 4 with CPLL | 116 | Fabric | [ 3] | [ 6] | [ 8] | [ 10] |
IIb | Y | 8 with CPLL | 117, 118 | Fabric | 3 | [ 6] | 8 | 10 |
IIb | Y | 20 with CPL | 112 - 116 | Fabric | 3 | [ 6] | 8 | 10 |
IIb | Y | 24 with CPLL | 213 - 218 | RTM | 3 | [ 6] | 8 | 10 |
IIb | Y | 24 with CPLL | 110, 111, 210 - 213 | RTM | 3 | [ 6] | 8 | 10 |
IIb | Y | 44 with CPLL | 111 - 119, 218, 219 | Fabric | [ 3] | [ 10] | ||
IIb | Y | 44 with QPLL | 111 - 119, 218, 219 | Fabric | [ 8] | [ 10] | ||
IIb | Y | 44 with CPLL | 110, 111, 210 - 218 | RTM | [ 3] | [ 6] | [ 8] | [ 10] |
IIb | y | 44 with QPLL | 110, 111, 210 - 218 | RTM | [ 8] | [ 10] | ||
IIb | Y | 80 with CPLL | All | [ 3] | [ 6] | [ 8] | [ 10] | |
IIb | Y | 80 with QPLL | All | [ 10] | ||||
IIb | N | 20 with CPLL | 112 - 116 | Fabric | [ 3] | [ 6] | [ 8] | [ 10] |
IIa | N | 1 with CPLL | GTX12 | Fabric | [ 3] | [ 6] | [ 8] | [ 10] |
IIa | Y( only work in Vivado) | 4 with CPLL | GTX12 - GTX15 | Fabric | [ 3] | [ 6] | [ 8] | [ 10] |
IBERT firmwares with GTH refrence CLK=125MHz | ||||||||
Pulsar | Vidado (Y/N) | # of channels | Channels | Usage | Speed (Gbps) | Speed (Gbps) | Speed (Gbps) | Speed (Gbps) |
IIb | Y | 44 with QPLL | 111 - 119, 218, 219 | Fabric | [ 6.25] | [ 8] | [ 10] [ 10.3125 with refclk156] | |
IIb | Y | 80 with QPLL | All | [ 6.25] | [ 8] | [ 10] |
logical ( physical* ) Slot# | 1 (7) | 2 (8) | 3 (6) | 4 (9) | 5 (5) | 6 (10) | 7 (4) | 8 (11) | 9 (3) | 10 (12) | 11 (2) | 12 (13) | 13 (1) | 14 (13) |
1 (7) | 117-2,-3, 118-0,-1 |
118-0,-1 | 118-0,-1 | 118-0,-1 | 118-0,-1 | 118-0,-1 | 118-0,-1 | 118-0,-1 | 118-0,-1 | 118-0,-1 | 118-0,-1 | 118-0,-1 | 118-0,-1 | |
2 (8) | 117-2,-3,118-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | 117-0,-1 | |
3 (6) | 117-0,-1 | 117-0,-1 | 116-2,-3 | 116-2,-3 | 116-2,-3 | 116-2,-3 | 116-2,-3 | 116-2,-3 | 116-2,-3 | 116-2,-3 | 116-2,-3 | 116-2,-3 | 116-2,-3 | |
4 (9) | 116-2,-3 | 116-2,-3 | 116-2,-3 | 116-0,-1 | 116-0,-1 | 116-0,-1 | 116-0,-1 | 116-0,-1 | 116-0,-1 | 116-0,-1 | 116-0,-1 | 116-0,-1 | 116-0,-1 | |
5 (5) | 116-0,-1 | 116-0,-1 | 116-0,-1 | 116-0,-1 | 115-2,-3 | 115-2,-3 | 115-2,-3 | 115-2,-3 | 115-2,-3 | 115-2,-3 | 115-2,-3 | 115-2,-3 | 115-2,-3 | |
6 (10) | 115-2,-3 | 115-2,-3 | 115-2,-3 | 115-2,-3 | 115-2,-3 | 115-0,-1 | 115-0,-1 | 115-0,-1 | 115-0,-1 | 115-0,-1 | 115-0,-1 | 115-0,-1 | 115-0,-1 | |
7 (4) | 115-0,-1 | 115-0,-1 | 115-0,-1 | 115-0,-1 | 115-0,-1 | 115-0,-1 | 114-2,-3 | 114-2,-3 | 114-2,-3 | 114-2,-3 | 114-2,-3 | 114-2,-3 | 114-2,-3 | |
8 (11) | 114-2,-3 | 114-2,-3 | 114-2,-3 | 114-2,-3 | 114-2,-3 | 114-2,-3 | 114-2,-3 | 114-0,-1 | 114-0,-1 | 114-0,-1 | 114-0,-1 | 114-0,-1 | 114-0,-1 | |
9 (3) | 114-0,-1 | 114-0,-1 | 114-0,-1 | 114-0,-1 | 114-0,-1 | 114-0,-1 | 114-0,-1 | 114-0,-1 | 113-2,-3 | 113-2,-3 | 113-2,-3 | 113-2,-3 | 113-2,-3 | |
10 (12) | 113-2,-3 | 113-2,-3 | 113-2,-3 | 113-2,-3 | 113-2,-3 | 113-2,-3 | 113-2,-3 | 113-2,-3 | 113-2,-3 | 113-0,-1 | 113-0,-1 | 113-0,-1 | 113-0,-1 | |
11 (2) | 113-0,-1 | 113-0,-1 | 113-0,-1 | 113-0,-1 | 113-0,-1 | 113-0,-1 | 113-0,-1 | 113-0,-1 | 113-0,-1 | 113-0,-1 | 112-2,-3 | 112-2,-3 | 112-2,-3 | |
12 (13) | 112-2,-3 | 112-2,-3 | 112-2,-3 | 112-2,-3 | 112-2,-3 | 112-2,-3 | 112-2,-3 | 112-2,-3 | 112-2,-3 | 112-2,-3 | 112-2,-3 | 112-0,-1 | 112-0,-1 | |
13 (1) | 112-0,-1 | 112-0,-1 | 112-0,-1 | 112-0,-1 | 112-0,-1 | 112-0,-1 | 112-0,-1 | 112-0,-1 | 112-0,-1 | 112-0,-1 | 112-0,-1 | 112-0,-1 | 111-2,-3 | |
14 (14) | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 | 111-2,-3 |
-- ZijunXu - 12 Apr 2014
I | Attachment | History | Action | Size | Date | Who | Comment |
---|---|---|---|---|---|---|---|
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ASIS_crate.gif | r1 | manage | 323.5 K | 2014-04-20 - 21:35 | HangYin | ASIS crate physical slots and logic slots number |
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BottomLayer.PNG | r1 | manage | 516.8 K | 2015-05-25 - 06:04 | ZijunXu | |
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CPLL_example_ibert_44ch_fab_10gbps.bit | r1 | manage | 28061.4 K | 2014-06-06 - 15:52 | ZijunXu | |
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Checklist.docx | r1 | manage | 19.0 K | 2016-06-23 - 21:20 | ZijunXu | Pulsar2b Checklist |
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Clock_X1.PNG | r1 | manage | 252.4 K | 2014-04-19 - 00:58 | ZijunXu | |
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Clock_X2.PNG | r1 | manage | 183.4 K | 2014-04-19 - 00:58 | ZijunXu | |
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Clock_X5.PNG | r1 | manage | 260.4 K | 2014-04-19 - 00:58 | ZijunXu | |
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ESD_Protected.svg | r1 | manage | 2.1 K | 2016-04-06 - 17:21 | ZijunXu | |
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FMC_IC.PNG | r1 | manage | 28.8 K | 2015-05-25 - 06:27 | ZijunXu | |
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FMC_Polarized_Cap.PNG | r1 | manage | 659.8 K | 2015-05-25 - 06:38 | ZijunXu | |
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FPGA_Done.png | r1 | manage | 119.6 K | 2014-04-26 - 07:22 | ZijunXu | |
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GND.PNG | r1 | manage | 331.1 K | 2014-04-18 - 22:25 | ZijunXu | |
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GTH_in_RTM.PNG | r1 | manage | 183.6 K | 2014-05-23 - 19:36 | ZijunXu | |
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IBERT_for_PulsarIIb.pdf | r1 | manage | 336.3 K | 2014-06-06 - 16:13 | ZijunXu | |
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P2b_LEDBlinker.bin | r1 | manage | 2583.6 K | 2016-05-03 - 21:19 | ZijunXu | |
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PL2b_All20Quad_ref125_10Gbps.bit | r1 | manage | 17387.2 K | 2016-04-21 - 16:39 | ZijunXu | Pulsar2b IBERT vivado 2015p4p2 |
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PL2b_All20Quad_ref156p25_10p3125Gbps.bit | r1 | manage | 17199.4 K | 2016-04-21 - 16:38 | ZijunXu | Pulsar2b IBERT vivado 2015p4p2 |
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PL2b_All20Quad_ref200_10Gbps.bit | r1 | manage | 17393.0 K | 2016-04-21 - 16:42 | ZijunXu | |
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PL2b_Fab_All_ref125_10Gbps.bit | r1 | manage | 9196.1 K | 2016-04-21 - 02:11 | ZijunXu | Pulsar2b IBERT by vivado 2015p4p2 |
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PL2b_Fab_Q113_ref125_10Gbps.bit | r1 | manage | 4574.3 K | 2016-04-21 - 02:12 | ZijunXu | Pulsar2b IBERT by vivado 2015p4p2 |
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PL2b_Fab_Q113_ref156p25_10p3125Gbps.bit | r1 | manage | 4708.4 K | 2016-04-21 - 02:12 | ZijunXu | Pulsar2b IBERT by vivado 2015p4p2 |
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PL2b_Fab_Q113_ref200_10Gbps.bit | r1 | manage | 4640.7 K | 2016-04-21 - 02:12 | ZijunXu | Pulsar2b IBERT by vivado 2015p4p2 |
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PL2b_Fab_Q11567_ref125_10Gbps.bit | r1 | manage | 5814.0 K | 2016-04-21 - 02:12 | ZijunXu | Pulsar2b IBERT by vivado 2015p4p2 |
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PL2b_LVDS_loopback_BERT.ltx | r1 | manage | 13.0 K | 2016-07-14 - 23:01 | ZijunXu | |
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PL2b_LVDS_loopback_BERT_100MHz_FMC1.bit | r1 | manage | 3094.3 K | 2016-07-14 - 23:01 | ZijunXu | |
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PL2b_LVDS_loopback_BERT_100MHz_FMC2.bit | r1 | manage | 2959.2 K | 2016-07-14 - 23:01 | ZijunXu | |
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PL2b_LVDS_loopback_BERT_100MHz_FMC3.bit | r1 | manage | 3094.0 K | 2016-07-14 - 23:01 | ZijunXu | |
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PL2b_LVDS_loopback_BERT_100MHz_FMC4.bit | r1 | manage | 3078.2 K | 2016-07-14 - 23:01 | ZijunXu | |
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Pulsar2B_testing.pdf | r3 r2 r1 | manage | 3564.0 K | 2014-05-27 - 18:40 | ZijunXu | |
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Pulsar2b_LEDBlinker.bit | r1 | manage | 2583.7 K | 2016-04-20 - 21:33 | ZijunXu | Pulsar2b_LEDBlinker vivado 2015p4p2 |
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QPLL_example_ibert_44ch_fab_10gbps.bit | r1 | manage | 28061.5 K | 2014-06-04 - 19:04 | ZijunXu | |
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QPLL_example_ibert_44ch_fab_8gbps.bit | r1 | manage | 28061.4 K | 2014-06-04 - 19:03 | ZijunXu | |
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QPLL_example_ibert_44ch_rtm_10gbps.bit | r1 | manage | 28061.5 K | 2014-06-04 - 19:08 | ZijunXu | |
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QPLL_example_ibert_44ch_rtm_8gbps.bit | r1 | manage | 28061.4 K | 2014-06-04 - 19:06 | ZijunXu | |
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QPLL_example_ibert_80ch_10gbps.bit | r1 | manage | 28061.4 K | 2014-06-06 - 15:54 | ZijunXu | |
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RTM2_GTHs.PNG | r1 | manage | 160.9 K | 2014-12-26 - 08:52 | ZijunXu | |
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RTM_v2p0.PNG | r1 | manage | 280.2 K | 2014-12-15 - 21:09 | ZijunXu | |
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RoutingTable.png | r1 | manage | 205.6 K | 2014-05-28 - 20:08 | ZijunXu | |
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TopLayer.PNG | r1 | manage | 409.5 K | 2015-05-25 - 06:05 | ZijunXu | |
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clock_setting.PNG | r3 r2 r1 | manage | 237.4 K | 2016-04-20 - 18:14 | ZijunXu | |
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clock_sw12.PNG | r1 | manage | 273.7 K | 2014-04-18 - 18:52 | ZijunXu | |
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crate_fullmesh.JPG | r1 | manage | 2173.1 K | 2014-05-27 - 18:34 | ZijunXu | |
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example_ibert_16ch_RTM_214_213_110_111_10.3125gbps_QPLL.bit | r1 | manage | 28061.4 K | 2014-06-30 - 22:54 | ZijunXu | |
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example_ibert_20ch_112_116_6gbps.bit | r1 | manage | 28061.4 K | 2014-04-29 - 16:55 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116. |
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example_ibert_24ch_210_213_110_111_6gbps.bit | r1 | manage | 28061.4 K | 2014-04-28 - 23:35 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, used for the RTM test with 24 activated channels (110, 111, 210 - 213), 6Gbps. |
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example_ibert_24ch_213_218_6gbps.bit | r1 | manage | 28061.4 K | 2014-04-28 - 23:32 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, used for the RTM test with 24 activated channels (213 - 218), 6Gbps. |
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example_ibert_44ch_fab_3gbps.bit | r1 | manage | 28061.4 K | 2014-04-24 - 17:47 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218). |
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example_ibert_44ch_rtm_10gbps.bit | r1 | manage | 28061.5 K | 2014-04-24 - 17:38 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218). |
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example_ibert_44ch_rtm_3gbps.bit | r1 | manage | 28061.4 K | 2014-04-24 - 17:42 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218). |
![]() |
example_ibert_44ch_rtm_6gbps.bit | r1 | manage | 28061.4 K | 2014-04-24 - 17:40 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218). |
![]() |
example_ibert_44ch_rtm_8gbps.bit | r1 | manage | 28061.4 K | 2014-04-24 - 17:39 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218). |
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example_ibert_4ch_116_10gbps.bit | r1 | manage | 28061.4 K | 2014-04-26 - 01:41 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116. |
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example_ibert_4ch_116_3gbps.bit | r1 | manage | 28061.4 K | 2014-04-26 - 01:44 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116. |
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example_ibert_4ch_116_6gbps.bit | r1 | manage | 28061.5 K | 2014-04-25 - 05:02 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116. |
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example_ibert_7series_11Quad_6p25G_ref125.bit | r1 | manage | 28061.5 K | 2014-11-24 - 21:01 | ZijunXu | |
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example_ibert_7series_11Quads_10Gbps_ref125.bit | r1 | manage | 28061.5 K | 2014-11-24 - 21:02 | ZijunXu | |
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example_ibert_7series_11Quads_8G_ref125.bit | r1 | manage | 28061.5 K | 2014-11-24 - 21:00 | ZijunXu | |
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example_ibert_7series_20Quads_10G_ref125.bit | r1 | manage | 28061.5 K | 2014-11-24 - 22:26 | ZijunXu | |
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example_ibert_7series_20Quads_10p3125_ref156.bit | r1 | manage | 16898.6 K | 2014-12-21 - 01:25 | ZijunXu | |
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example_ibert_7series_20Quads_6p25G_ref125.bit | r1 | manage | 28061.5 K | 2014-12-15 - 17:05 | ZijunXu | |
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example_ibert_7series_20Quads_8G_ref125.bit | r1 | manage | 28061.5 K | 2014-12-08 - 21:06 | ZijunXu | |
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example_ibert_80ch_10gbps.bit | r1 | manage | 28061.4 K | 2014-04-24 - 17:56 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature. |
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example_ibert_80ch_3gbps.bit | r1 | manage | 28061.4 K | 2014-04-24 - 18:00 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature. |
![]() |
example_ibert_80ch_6gbps.bit | r1 | manage | 28061.4 K | 2014-04-24 - 17:57 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature. |
![]() |
example_ibert_80ch_8gbps.bit | r1 | manage | 28061.4 K | 2014-04-24 - 17:59 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature. |
![]() |
example_ibert_8ch_117_118_6gbps.bit | r1 | manage | 28061.4 K | 2014-04-28 - 23:30 | HangYin | Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, used for the backplane test with 8 activated channels (117, 118), 6Gbps. |
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example_ibert_bank_113.bit | r1 | manage | 28061.4 K | 2014-05-09 - 17:12 | ZijunXu | ibert firmware for VC709 bank 113, with 10.3125Gbps |
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example_ibert_pulsarIIa_QPLL_allchannels_6p25Gbps.bit | r1 | manage | 11175.5 K | 2014-06-17 - 22:16 | ZijunXu | |
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example_ibert_pulsarIIa_allchannels_10Gbps.bit | r1 | manage | 11175.5 K | 2014-06-25 - 00:02 | ZijunXu | |
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example_ibert_pulsarIIa_allchannels_8Gbps.bit | r2 r1 | manage | 11175.5 K | 2014-06-25 - 01:05 | ZijunXu | |
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example_ibert_q118_10gbps.bit | r1 | manage | 11175.5 K | 2014-04-26 - 01:38 | HangYin | Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with different Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb. |
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example_ibert_q118_3gbps.bit | r1 | manage | 11175.5 K | 2014-04-26 - 01:36 | HangYin | Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with 6 Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb. |
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example_ibert_q118_6gbps.bit | r1 | manage | 11175.5 K | 2014-04-24 - 17:28 | HangYin | Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with 6 Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb. |
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example_ibert_q118_8gbps.bit | r1 | manage | 11175.5 K | 2014-04-26 - 01:39 | HangYin | Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with different Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb. |
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example_ibert_vertex7_gth_112_116_10gbps.bit | r1 | manage | 28061.5 K | 2014-04-24 - 18:18 | HangYin | ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116. |
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example_ibert_vertex7_gth_112_116_3gbps.bit | r1 | manage | 28061.5 K | 2014-04-24 - 18:22 | HangYin | ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116. |
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example_ibert_vertex7_gth_112_116_6gbps.bit | r1 | manage | 28061.5 K | 2014-04-24 - 18:21 | HangYin | ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116. |
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example_ibert_vertex7_gth_112_116_8gbps.bit | r1 | manage | 28061.5 K | 2014-04-24 - 18:20 | HangYin | ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116. |
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example_ibert_vertex7_gth_116_10gbps.bit | r1 | manage | 28061.5 K | 2014-04-24 - 18:58 | HangYin | ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116. |
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example_ibert_vertex7_gth_116_3gbps.bit | r1 | manage | 28061.5 K | 2014-04-24 - 19:03 | HangYin | ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116. |
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example_ibert_vertex7_gth_116_3gbps_correct_clock.bit | r1 | manage | 28061.5 K | 2014-04-29 - 21:57 | HangYin | ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116. |
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example_ibert_vertex7_gth_116_6gbps.bit | r1 | manage | 28061.5 K | 2014-04-24 - 19:01 | HangYin | ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116. |
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example_ibert_vertex7_gth_116_8gbps.bit | r1 | manage | 28061.5 K | 2014-04-24 - 18:59 | HangYin | ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116. |
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example_pulsar2a_ibert_gtx12_10gbps.bit | r1 | manage | 11175.6 K | 2014-04-25 - 00:47 | HangYin | ISE only! For Pulsar IIa FPGA programming, with the external clock frequency, GTX12 activated. |
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example_pulsar2a_ibert_gtx12_3gbps.bit | r1 | manage | 11175.6 K | 2014-04-25 - 00:49 | HangYin | ISE only! For Pulsar IIa FPGA programming, with the external clock frequency, GTX12 activated. |
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example_pulsar2a_ibert_gtx12_6gbps.bit | r1 | manage | 11175.6 K | 2014-05-07 - 23:04 | HangYin | |
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example_pulsar2a_ibert_gtx12_8gbps.bit | r1 | manage | 11175.6 K | 2014-04-25 - 00:48 | HangYin | ISE only! For Pulsar IIa FPGA programming, with the external clock frequency, GTX12 activated. |
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fuses.PNG | r1 | manage | 425.1 K | 2016-04-19 - 20:14 | ZijunXu | |
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jumper_fmc.png | r2 r1 | manage | 213.8 K | 2014-04-18 - 19:09 | ZijunXu | |
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jumper_fmc2.png | r1 | manage | 3.9 K | 2014-04-24 - 17:12 | ZijunXu | |
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jumper_zone1.png | r2 r1 | manage | 268.4 K | 2014-04-18 - 19:09 | ZijunXu | |
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jumper_zone3.png | r2 r1 | manage | 367.1 K | 2014-04-18 - 19:09 | ZijunXu | |
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main.bit | r2 r1 | manage | 2640.6 K | 2014-04-26 - 18:03 | ZijunXu | |
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mezz.bit | r2 r1 | manage | 630.7 K | 2014-04-26 - 18:03 | ZijunXu | |
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polarized_Capacitors.PNG | r1 | manage | 318.2 K | 2014-04-18 - 17:31 | ZijunXu | |
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polarized_Capacitors2.PNG | r1 | manage | 295.8 K | 2014-04-18 - 17:31 | ZijunXu | |
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pulsar2b_initial_test.tar.gz | r1 | manage | 85.2 K | 2014-04-25 - 08:33 | HangYin | framework |
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refclock_assignment.png | r1 | manage | 414.4 K | 2014-04-26 - 22:44 | ZijunXu | |
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resistor_distri.PNG | r1 | manage | 305.2 K | 2014-05-25 - 00:53 | ZijunXu | |
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rtm_connector.png | r2 r1 | manage | 101.2 K | 2014-04-26 - 01:08 | ZijunXu | |
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rtm_power.png | r2 r1 | manage | 159.0 K | 2014-07-09 - 00:47 | ZijunXu | |
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rtm_power2.png | r1 | manage | 11.8 K | 2014-04-26 - 00:58 | ZijunXu | |
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valtage_12_U16.PNG | r2 r1 | manage | 121.0 K | 2014-05-27 - 18:07 | ZijunXu | |
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valtage_12_U171821.PNG | r3 r2 r1 | manage | 207.7 K | 2014-07-09 - 00:43 | ZijunXu | |
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valtage_12_U23.PNG | r2 r1 | manage | 137.6 K | 2014-05-27 - 18:17 | ZijunXu | |
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valtage_1_U17.PNG | r1 | manage | 256.5 K | 2014-04-18 - 23:25 | ZijunXu | |
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valtage_1_U21.PNG | r1 | manage | 255.3 K | 2014-04-18 - 23:28 | ZijunXu | |
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valtage_1p0_fpga.PNG | r1 | manage | 293.3 K | 2014-04-19 - 00:48 | ZijunXu | |
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valtage_1p2_U23.PNG | r1 | manage | 190.6 K | 2014-04-18 - 23:31 | ZijunXu | |
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valtage_1p5_U22.PNG | r1 | manage | 211.6 K | 2014-04-19 - 00:29 | ZijunXu | |
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valtage_1p5_fpga.PNG | r1 | manage | 285.6 K | 2014-04-19 - 00:27 | ZijunXu | |
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valtage_1p8_U18.PNG | r1 | manage | 371.6 K | 2014-04-18 - 23:54 | ZijunXu | |
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valtage_1p8_U29.PNG | r1 | manage | 235.1 K | 2014-04-19 - 00:37 | ZijunXu | |
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valtage_1p8_fpga.PNG | r1 | manage | 289.8 K | 2014-04-19 - 00:44 | ZijunXu | |
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valtage_3p3_U16.PNG | r1 | manage | 267.0 K | 2014-04-18 - 23:18 | ZijunXu | |
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valtage_pim3p3.PNG | r2 r1 | manage | 104.0 K | 2014-05-27 - 18:04 | ZijunXu | |
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vivado_FMCLoop_scan.tcl | r1 | manage | 2.9 K | 2016-07-14 - 23:01 | ZijunXu | |
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vivado_FMCLoop_setup.tcl | r1 | manage | 12.5 K | 2016-07-14 - 23:01 | ZijunXu | |
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vivado_fabric_scan.tcl | r1 | manage | 4.3 K | 2016-04-21 - 02:27 | ZijunXu | |
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vivado_fabric_setup.tcl | r2 r1 | manage | 7.6 K | 2016-07-14 - 23:07 | ZijunXu | |
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vivado_rtms_scan.tcl | r1 | manage | 9.2 K | 2016-07-21 - 18:50 | ZijunXu | |
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vivado_rtms_setup.tcl | r1 | manage | 14.6 K | 2016-07-21 - 18:50 | ZijunXu | |
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voltage_summary.PNG | r2 r1 | manage | 329.4 K | 2014-04-24 - 18:01 | ZijunXu | |
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xilinx_FPGA.JPG | r2 r1 | manage | 38.5 K | 2016-07-14 - 21:31 | ZijunXu | from http://www.xilinx.com/support/documentation/errata/en206.pdf![]() |