Completed Checklist for a new Pulsar IIb baord

Useful Information

Checklist for download: Checklist.docx

Documentations

• Pulsar IIb prototype web page (ATCA @ Fermilab)
• More details for checking: Pulsar2B_testing.pdf
• Pulsar2a testing

Anti-Static

• [ ] Before touching any boards/devices, using an anti-static wrist strap to keep your partner and yourself grounded;
• [ ] When moving any boards/devices, using anti-static bags or boxes;

Visual Testing

• [ ] Pulsar2b is compatible with different types of xilinx Virtex-7 FPGA in the FFG1927 package:
  • [ ]XC7VX690T (80 GTX, default for CMS L1 Tracking Trigger project)
  • [ ]XC7VX550T (80 GTX);
  • [ ]XC7VX485T (56 GTX, Quads 113-119 & 213-219)
  • [ ]XC7VX415T (48 GTX, Quads 114-119 & 214-219)
  • 

• [ ] Soldering quality: Solder joints should have a smooth appearance. A satin luster is permissible. The joints should be free from scratches, sharp edges, grittiness, looseness, blistering, or other evidence of poor workmanship. more details about soldering
• [ ] *note: R72 and R80 should be empty
• [ ] Orientation of IC's: see small ticks around the IC's;
• [ ] all fuses are installed
  • F1, F2: 0.5A
  • F3, F4, F5, F6: 10A
  • 
• [ ] polarity of capacitors:
  • 
• [ ] Measure the resistance value between 5 test points of GND. They should be 0~0.1 Ω.
  • 
• [ ] Measure the resistance value between power rails to GND
  • 
  • The observed values could be different by 50% or more from reference value. It's safe if the observed value is larger than the reference value. But if the observed value is too small, please contract experts.
  • make sure the resistance value is far from 0. Be more careful about the VCC1V0.

Power Rails	Referece Value(Ω)	Observed Value(Ω)
P1 VCC12	3.5K
P2 VCC3V3	3.0K
P3 VCC1V0	14.2
P4 MGTAVCC 1.0V	111
P5 MGTAVTT 1.2V	2.5K or 350
P6 VCC1V8	650
P7 MGTAVCCAUX 1.8V	6.5K
P8 VCC1V5	511

• • [ ] P1 VCC12 (from Power Converter U9): input for U16, U17, U18, U21, and U23;
  • 
  • [ ] P2 VCC3V3: testing point (output of U16, 20A)
  • 
  • [ ] P3 VCC1V0 testing point(VCCINT, CVVBRAM, output of U17, 40A)
  • 
  • [ ] P4 MGTVACC : testing point (MGTVACC, output of U21, input of FPGA, 40A):
  • 
  • [ ] P5 MGTAVTT :testing point (MGTAVTT, output of U23, 20A):
  • 
  • [ ] P6 VCC1V8 : testing point (VCCAUX, VCCO, VCCAUX_IO, output of U18, input of FPGA, 6A)
  • 
  • [ ] P7 MGTVCCAUX (MGTVCCAUX, output of U29, 3A)
  • 
  • [ ] P8 VCC1V5 (VCCO, DDR3, output of U22, input of FPGA, 3A)
  • 

• [ ] Measure these resistors for each Power Regulators :
  • U16: R22, R26, R28, R29;
  • U17: R23, R27, R30,R31;
  • U18: R24, R25, R32, R33;
  • U21: R34, R36, R38, R39;
  • U23: R35, R37, R40, R41.
  • All the resistor listed above are in the back of pulsarIIb board:
  • 
  • (Note, the reference values are observed values from pulsarIIb board 3, as a reference.)

Regulator	Resistor	Schematic Value (Ω)	Reference Value(Ω)	Observed Value(Ω)
U16	R22	240	242
	R26	4.2k	4.19k
	R28	10k	10.05k
	R29	36.5k	36.2k
U17	R23	240	242
	R27	30.0k	19.7k
	R30	23.7k	23.5k
	R31	23.7k	23.4k
U18	R24	240	242
	R25	10k	8.88k
	R32	23.7k	23.5k
	R33	36.5k	36.4k
U21	R34	240	242
	R36	30.0k	19.6k
	R38	36.5k	36.2k
	R39	23.7k	23.5k
U23	R35	240	242
	R37	20.0k	15.8k
	R40	10k	10.05k
	R41	23.7k	23.5k

• [ ] Set Dip Switches (SW1,SW2) to 125MHz which is the default GTH reference clock frequence
  • Set the dip switches to 125 MHz configuration as default: {1, 1, 1, 1, 0, "X"} = {PR1, PR0, OD0, OD1, OD2, OPT}
  • Note: the "OPT" pin is not used to clock frequency configuration;
  • Note: both of the two switches are used for FPGA GTH reference clock;
  • Typical configuration are summerized below, more details please check the data sheet of CDCM61004;
  • 
• [ ] Check the jumpers:
  • Zone 1 jumper (JP2):
    • OFF = IPMC CONTROL; ON = FORCE 12V ON;
    • When there is no IPMC, turn on to force 12V on;
    • 
  • 4 FMC jumpers (JP1-FMC1,2,3,4):
    • 1-2: BYPASS; 2-3: NORMAL;
    • when there is NO FMC mezzanine card, need to bypass this FMC connecter. 1 jumper as example:
    • 
  • Zone3 jumpers (JP3, JP4):
    • ON = IPMC CONTROL; OFF = FORCE ON; (opposite to Zone1 jumper JP2)
    • when there is no IPMC, OFF to force RTM power on:
    • 
• [ ] Installing a proper heat sink to the Pulsar2b FPGA, and preparing a fan for cooling;

Voltages Testing

• [ ] Use anti-static wrist strap to ground yourself.
• [ ] Using the 1U ATCA crate for testing. (if you only have a mini-backplane for testing, then, setup the mini backplan with proper voltage applied.(recommend 48V , can work from 36V to 72V, ) )
• [ ] Turn on the fan for cooling.
  Initial configuration for the first testing:
• [ ] No IPMC
• [ ] No RTM;
• [ ] No FMC, so JP1-FMC1,2,3,4 set to bypass(connect 1-2);
  At first, testing the management voltage:
• [ ] Without IPMC mezzanine card, but turn JP2 off, so the 12V voltage are off, while the management voltage (3.3V from PIM) still on:
• 
• [ ] After this test, turn off the main voltage.
• [ ] Check all jumpers' pin status again.
  • [ ] without IPMC mezzanine card, JP2 ON, JP3 OFF, JP4 OFF;
• [ ] Turn on the main voltage.
  • Note: immediately 12V will be on and all the voltage will be activated;
  • Note: hot swap handle do not work without IPMC card. Turning off the main voltage will directly turn off the pulsar2b board.
• [ ] Check current value (before FPGA is programmed);
• [ ] Probe voltage of several points to check if they are expected:
  • [ ] 5 test points of GND:
  • 
  • Note: Summary of positions of power regulators:
  • 
  • Note: the difference between observed value and expected value should be less than 0.5%

Power Rails	Observed Voltage(V)
P1 VCC12
P2 VCC3V3
P3 VCC1V0
P4 MGTAVCC 1.0V
P5 MGTAVTT 1.2V
P6 VCC1V8
P7 MGTAVCCAUX 1.8V
P8 VCC1V5
RTM (12V)

• • [ ] VCC12 (from Power Converter U9): input for U16, U17, U18, U21, and U23;
    • U16: C103, C104
    • 
    • U17: C115, C117, and C118; U18: C110 and C111; U21: C107 and C108;
    • 
    • U23: C119, C121,and C122;
    • 
  • [ ] VCC3V3: testing point (output of U16, 20A)
  • 
  • [ ] VCC1V0 testing point(VCCINT, CVVBRAM, output of U17, 40A)
  • 
  • [ ] VCC1V0 : testing point (MGTVACC, output of U21, input of FPGA, 40A):
  • 
  • [ ] VCC1V2 :testing point (MGTATT, output of U23, 20A):
  • 
  • [ ] VCC1V8 : testing point (VCCAUX, VCCO, VCCAUX_IO, output of U18, input of FPGA, 6A)
  • 
  • [ ] VCC1V5 (VCCO, DDR3, output of U22, input of FPGA, 3A)
  • 
  • [ ] VCC1V8 (MGTVCCAUX, output of U29, 3A)
  • Note: this pin should be probed, be careful not to have short circuit!!)
  • 
  • [ ] Probe the power output from Pulsar IIb board zone-3:
    • 12V at D10, which is a schottky rectifier
    • 

First LED Blinking Test

• [ ] Check 4 FMC jumpers( JP1-FMC1,2,3,4) connection before JTAG programming: if there is no FMC card, to connect 1-2 to bypass this FMC connector.
• [ ] Programming FPGA with the LED blinker firmware: Pulsar2b_LEDBlinker.bit:
  • [ ] Check the DONE LED( D1): Blue color
    • 
  • [ ] Take care for temperature when you program new firmware ALWAYS (SET 75C^o as up limit).
  • [ ] There are four LEDs in frond panel, if input clock frequency is A MHz, for example 200 MHz:
    • 1st LED : A*1e6/2^(25+1) = 2.98 Hz
    • 2nd LED: A*1e6/2^(26+1) = 1.49 Hz
    • 3rd LED : A*1e6/2^(27+1) =0.745 Hz
    • 4th LED : A*1e6/2^(28+1) =0.373 Hz
• [ ] store the firmware into SPI memory
  • firmware: P2b_LEDBlinker.bin
  • SPI memory type: n25q256-1.8v-spi-x1_x2_x4

IBERT Test

Set the reference clock to 125MHz, GTH speed is 10.0Gbps

[ ] 4 GTHs (Quad-113) at 10Gbps: PL2b_Fab_Q113_ref125_10Gbps.bit

[ ] 12 GTHs ( Quad-115,116,117) at 10Gbps: PL2b_Fab_Q11567_ref125_10Gbps.bit

[ ] 32 GTHs ( Quad-111 to Quad-118) at 10Gbps: PL2b_Fab_All_ref125_10Gbps.bit. All the 28 channels for Fabric Interface could be test by this firmware;

[ ] 80 GTHs ( Quad-210 to Quad-219, and Quad-110 to Quad-119) at 10Gbps: PL2b_All20Quad_ref125_10Gbps.bit. All the 80 GTHs could be test by this firmware;

Vivado TCL scripts for testing fabric interface: vivado_fabric_setup.tcl, vivado_fabric_scan.tcl;

for FMC loopback: vivado_FMCLoop_setup.tcl, vivado_FMCLoop_scan.tcl;

for RTM test: vivado_rtms_setup.tcl, vivado_rtms_scan.tcl

Set the reference clock to 200MHz, GTH speed is 10.0Gbps

[ ] 4 GTHs( Quad-113) at 10Gbps: PL2b_Fab_Q113_ref200_10Gbps.bit;

[ ] 80 GTHs ( Quad-210 to Quad-219, and Quad-110 to Quad-119) at 10Gbps: PL2b_All20Quad_ref200_10Gbps.bit

Set the reference clock to 156.25MHZ, GTH speed is 10.3125Gbps

[ ] 4 GTHs( Quad-113) at 10.3125Gbps: PL2b_Fab_Q113_ref156p25_10p3125Gbps.bit

[ ] 80 GTHs ( Quad-210 to Quad-219, and Quad-110 to Quad-119) at 10Gbps: PL2b_All20Quad_ref156p25_10p3125Gbps.bit

Note1: 28 GTHs used for Fabric: Quad-111-2 to Quad-118-1 (or X1Y6 to X1Y33)

Note2: 12(=3x4) GTHs used for FMC cards (1 to 4) are: [219-3,219-2,219-1], [219-0, 218-3,218-2], [118-2,118-3,119-0], [119-1,119-2,119-3]; (or [X0Y39 to X0Y37 ], [X0Y36 to X0Y34 ], [X1Y34 to X1Y36 ], [X1Y37 to X1Y39 ])

Note3: The rest 40 GTHs used for RTM;

FMC LVDS

Firmware for testing the FMC lvds channels with FMC loopback cards:

PL2b_LVDS_loopback_BERT_100MHz_FMC1.bit,

PL2b_LVDS_loopback_BERT_100MHz_FMC2.bit,

PL2b_LVDS_loopback_BERT_100MHz_FMC3.bit,

PL2b_LVDS_loopback_BERT_100MHz_FMC4.bit,

and PL2b_LVDS_loopback_BERT.ltx.

Appendix

Introduction of how to use vivado to do ibert testing: link

8 Reference Clock assignment for GTH:

RefClk 0	MGTREFCLK0_118
RefClk 1	MGTREFCLK0_115
RefClk 2	MGTREFCLK0_219
RefClk 3	MGTREFCLK0_112
RefClk 4	MGTREFCLK0_110
RefClk 5	MGTREFCLK0_211
RefClk 6	MGTREFCLK0_214
RefClk 7	MGTREFCLK0_217

Below is a summary of which Reference Clock could be used for each GTH

GTH	Ref Clk
210	MGTREFCLK0_211
211	MGTREFCLK0_211
212	MGTREFCLK0_211
213	MGTREFCLK0_214
214	MGTREFCLK0_214
215	MGTREFCLK0_214
216	MGTREFCLK0_217
217	MGTREFCLK0_217
218	MGTREFCLK0_217, 219
219	MGTREFCLK0_219
110	MGTREFCLK0_110
111	MGTREFCLK0_110, 112
112	MGTREFCLK0_112
113	MGTREFCLK0_112
114	MGTREFCLK0_115
115	MGTREFCLK0_115
116	MGTREFCLK0_115
117	MGTREFCLK0_118
118	MGTREFCLK0_118
119	MGTREFCLK0_118

Below is GTHs assignments of the old version RTM, which was mounted with QSFP+ and SFP+ modules. (213-2 and 111-1 are not connected)

Below is the RTM v2.0 GTHs assignments:

28 GTHs used for Fabric: GTX111-2 to GTX118-1. In new mini-backplane, GTX118-1 is connected to SFP+ connector, other are looped back.

12(=3x4) GTHs used for FMC cards(1 to 4) are: [219-3,219-2,219-1], [219-0, 218-3,218-2], [118-2,118-3,119-0], [119-1,119-2,119-3];

Summary of the GTH channals have been reversed: ("R"=reversed, "-" = normal )

GTH	TX	RX
GTX211_2 (RTM)	R	-
GTX212_2 (RTM)	-	R
GTX212_3 (RTM)	R	-
GTX214_0 (RTM)	-	R
GTX218_3 (FMC)	R	-
GTX219_1 (FMC)	-	R
GTX219_2 (FMC)	-	R
GTX219_3 (FMC)	R	R
GTX110_0 (RTM)	R	R
GTX110_1 (RTM)	R	R
GTX110_2 (RTM)	R	R
GTX110_3 (RTM)	R	R
GTX111_0 (RTM)	R	-
GTX111_2 (fab)	R	-
GTX114_3 (fab)	-	R
GTX118_2 (FMC)	-	R
GTX119_1 (FMC)	R	R
GTX119_2 (FMC)	R	-
GTX119_3 (FMC)	-	R

FPGA IBERT testing start:

• [ ] Make sure the clock frequency is setting to 200 MHZ for both Pulsar IIa and Pulsar IIb boards
• [ ] Note: start from mini-backplane with good cooling;
• [ ] Note: start from small number of GTHs and low speed (6Gbps as start point);
• [ ] Note: check current and temperature when increasing number of GTH;
• [ ] Check the functionality with internal LOOP back (to check functionality firmware programming / clock distribution etc)
• [ ] Check the functionality with external LOOP back with as many pattern as possible
  • NOTE : step-by-step from single FPGA standalone, loop back at the other FPGA (so-called far-end Loop back mentioned in Figure 2-26 of UG476) with two board
• [ ] Check the error rate (~ E-014, 20 mins running) and 2-D eye diagrams for each channels
• [ ] IBERT firmwares

IBERT firmwares with GTH refrence CLK=200MHz
Pulsar	Vidado (Y/N)	# of channels	Channels	Usage	Speed (Gbps)	Speed (Gbps)	Speed (Gbps)	Speed (Gbps)
IIb	Y	4 with CPLL	116	Fabric	[ 3]	[ 6]	[ 8]	[ 10]
IIb	Y	8 with CPLL	117, 118	Fabric	3	[ 6]	8	10
IIb	Y	20 with CPL	112 - 116	Fabric	3	[ 6]	8	10
IIb	Y	24 with CPLL	213 - 218	RTM	3	[ 6]	8	10
IIb	Y	24 with CPLL	110, 111, 210 - 213	RTM	3	[ 6]	8	10
IIb	Y	44 with CPLL	111 - 119, 218, 219	Fabric	[ 3]			[ 10]
IIb	Y	44 with QPLL	111 - 119, 218, 219	Fabric			[ 8]	[ 10]
IIb	Y	44 with CPLL	110, 111, 210 - 218	RTM	[ 3]	[ 6]	[ 8]	[ 10]
IIb	y	44 with QPLL	110, 111, 210 - 218	RTM			[ 8]	[ 10]
IIb	Y	80 with CPLL		All	[ 3]	[ 6]	[ 8]	[ 10]
IIb	Y	80 with QPLL		All				[ 10]
IIb	N	20 with CPLL	112 - 116	Fabric	[ 3]	[ 6]	[ 8]	[ 10]
IIa	N	1 with CPLL	GTX12	Fabric	[ 3]	[ 6]	[ 8]	[ 10]
IIa	Y( only work in Vivado)	4 with CPLL	GTX12 - GTX15	Fabric	[ 3]	[ 6]	[ 8]	[ 10]
IBERT firmwares with GTH refrence CLK=125MHz
Pulsar	Vidado (Y/N)	# of channels	Channels	Usage	Speed (Gbps)	Speed (Gbps)	Speed (Gbps)	Speed (Gbps)
IIb	Y	44 with QPLL	111 - 119, 218, 219	Fabric		[ 6.25]	[ 8]	[ 10] [ 10.3125 with refclk156]
IIb	Y	80 with QPLL		All		[ 6.25]	[ 8]	[ 10]

Vivado + Pulsar IIa firmware [ details] Vivado + Pulsar IIb firmware details]

Could connect RTM with Vertex 7 Evaluation kit, so we can seperate Tx and Rx effects. vc709 firmware for bank113: 10.3125 Gbps, PulsarIIb firmware for RTM SFP+ channels: 10.3125 Gbps

ps: please change pulsarIIb SW1 and SW2 to 156.25MHz.

PulsarIIa 6.25 Gbps firmware , 8Gbps firmware, and 10Gbps firmware from ISE with SYSCLK=200MHz, RefCLK =125MHZ.

Note:

1) introduction of making IBERT farmware for PulsarIIb : here

GTX LOOP back test

• [ ] RTM QSFP+, SFP+ loopback test . GTX110_0 to GTX111_1, and GTX210_0 to GTX218_1
• [ ] Fabric backplane test: to be developed. GTX111_2 to GTX118_1

FMC (FPGA Mezzanine card) v2.0 test

More details is here: Link

• [ ] Clock forwarding test: from pulsar2b main FPGA to mezzanine card FPGA;
  • Program Pulsar IIb FPGA with [ firmware]; (btw, this firmware is same one of the LED blinking test.)
  • Program mezzanine card FPGA with [ firmware].

Insertion to ATCA shelf

You can find the connection channel between any two slots in below table:

logical ( physical* ) Slot#	1 (7)	2 (8)	3 (6)	4 (9)	5 (5)	6 (10)	7 (4)	8 (11)	9 (3)	10 (12)	11 (2)	12 (13)	13 (1)	14 (13)
1 (7)		117-2,-3, 118-0,-1	118-0,-1	118-0,-1	118-0,-1	118-0,-1	118-0,-1	118-0,-1	118-0,-1	118-0,-1	118-0,-1	118-0,-1	118-0,-1	118-0,-1
2 (8)	117-2,-3,118-0,-1		117-0,-1	117-0,-1	117-0,-1	117-0,-1	117-0,-1	117-0,-1	117-0,-1	117-0,-1	117-0,-1	117-0,-1	117-0,-1	117-0,-1
3 (6)	117-0,-1	117-0,-1		116-2,-3	116-2,-3	116-2,-3	116-2,-3	116-2,-3	116-2,-3	116-2,-3	116-2,-3	116-2,-3	116-2,-3	116-2,-3
4 (9)	116-2,-3	116-2,-3	116-2,-3		116-0,-1	116-0,-1	116-0,-1	116-0,-1	116-0,-1	116-0,-1	116-0,-1	116-0,-1	116-0,-1	116-0,-1
5 (5)	116-0,-1	116-0,-1	116-0,-1	116-0,-1		115-2,-3	115-2,-3	115-2,-3	115-2,-3	115-2,-3	115-2,-3	115-2,-3	115-2,-3	115-2,-3
6 (10)	115-2,-3	115-2,-3	115-2,-3	115-2,-3	115-2,-3		115-0,-1	115-0,-1	115-0,-1	115-0,-1	115-0,-1	115-0,-1	115-0,-1	115-0,-1
7 (4)	115-0,-1	115-0,-1	115-0,-1	115-0,-1	115-0,-1	115-0,-1		114-2,-3	114-2,-3	114-2,-3	114-2,-3	114-2,-3	114-2,-3	114-2,-3
8 (11)	114-2,-3	114-2,-3	114-2,-3	114-2,-3	114-2,-3	114-2,-3	114-2,-3		114-0,-1	114-0,-1	114-0,-1	114-0,-1	114-0,-1	114-0,-1
9 (3)	114-0,-1	114-0,-1	114-0,-1	114-0,-1	114-0,-1	114-0,-1	114-0,-1	114-0,-1		113-2,-3	113-2,-3	113-2,-3	113-2,-3	113-2,-3
10 (12)	113-2,-3	113-2,-3	113-2,-3	113-2,-3	113-2,-3	113-2,-3	113-2,-3	113-2,-3	113-2,-3		113-0,-1	113-0,-1	113-0,-1	113-0,-1
11 (2)	113-0,-1	113-0,-1	113-0,-1	113-0,-1	113-0,-1	113-0,-1	113-0,-1	113-0,-1	113-0,-1	113-0,-1		112-2,-3	112-2,-3	112-2,-3
12 (13)	112-2,-3	112-2,-3	112-2,-3	112-2,-3	112-2,-3	112-2,-3	112-2,-3	112-2,-3	112-2,-3	112-2,-3	112-2,-3		112-0,-1	112-0,-1
13 (1)	112-0,-1	112-0,-1	112-0,-1	112-0,-1	112-0,-1	112-0,-1	112-0,-1	112-0,-1	112-0,-1	112-0,-1	112-0,-1	112-0,-1		111-2,-3
14 (14)	111-2,-3	111-2,-3	111-2,-3	111-2,-3	111-2,-3	111-2,-3	111-2,-3	111-2,-3	111-2,-3	111-2,-3	111-2,-3	111-2,-3	111-2,-3

In this table, the logical slot# in column is RX(receiver), and slot# in row is TX(transmitter). and like "116-0,-1" denots " 116-0 and 116-1".

* the mapping between physical number and logical number is depending on the shelf design. For same logical slot number, different shelfs may have different physical number.

Quad_210: MGT_X0Y0, X0Y1, X0Y2, X0Y3

Quad_211: MGT_X0Y4, X0Y5, X0Y6, X0Y7

Quad_212: MGT_X0Y8, X0Y9, X0Y10, X0Y11

Quad_213: MGT_X0Y12, X0Y12, X0Y14, X0Y15

Quad_214: MGT_X0Y16, X0Y17, X0Y18, X0Y19

Quad_215: MGT_X0Y20, X0Y21, X0Y22, X0Y23

Quad_216: MGT_X0Y24, X0Y25, X0Y26, X0Y27

Quad_217: MGT_X0Y28, X0Y29, X0Y30, X0Y31

Quad_218: MGT_X0Y32, X0Y33, X0Y34, X0Y35

Quad_219: MGT_X0Y36, X0Y37, X0Y38, X0Y39

Quad_110: MGT_X1Y0, X1Y1, X1Y2, X1Y3

Quad_111: MGT_X1Y4, X1Y5, X1Y6, X1Y7

Quad_112: MGT_X1Y8, X1Y9, X1Y10, X1Y11

Quad_113: MGT_X1Y12, X1Y13, X1Y14, X1Y15

Quad_114: MGT_X1Y16, X1Y17, X1Y18, X1Y19

Quad_115: MGT_X1Y20, X1Y21, X1Y22, X1Y23

Quad_116: MGT_X1Y24, X1Y25, X1Y26, X1Y27

Quad_117: MGT_X1Y28, X1Y29, X1Y30, X1Y31

Quad_118: MGT_X1Y32, X1Y33, X1Y34, X1Y35

Quad_119: MGT_X1Y36, X1Y37, X1Y38, X1Y39

• [ ] This step must after comfirmation with minibackplane.
• [ ] First is to test one board with internel loopback; Then to do the combined test with pulsar2a;
• [ ] Take the other baord off, and put the new board to ATCA and turn on: Pulsar IIa and Pulsar IIb in Slot-3 and Slot-4
  • 

• [ ] Program Pulsar IIa board with MGT12 [ bit file], for both top and bottom FPGAs.
  • a short note for the firmware design: http://hep.uchicago.edu/~okumura/works/pics/20140423/ibert_pulsar2A/README.txt">link.
• [ ] Program Pulsar IIb board with GTH116 [ bit file]
• [ ] Access to the FPGA through the ChipScope use the GUI, check the links between FPGAs
• [ ] Check Fabric Interface, Base Interface, Management Interface etc.

• [ ] Clock probing points::
  • SYSCLOCK (X5), 200 MHz (5ns period);
  • 
  • crystal oscillator (25MHz) {X1, X2};
  • 

RTM Power Test

• [ ] Probe the power output from Pulsar IIb board zone-3:
  • 12V at D10, which is a schottky rectifier
  • 
  • 12V power and 3.3V manage power inside the blue connector:
    • Only probe the orange pins, not touch the black pins;
      • • A1: 0V. It's Manage Power, only when RTM connected, it's 3.3V;
        • A2: GND;
        • A3: 12V;
        • A4: GND;
        • B2: 3.3V(PNs) when RTM is disconnected;
        • B3: 12V;
        • B4: GND
    • black pins:
      • • B1: ENABLEn
        • C1: SCL_L
        • C2: SDA_L
        • C3, C4, D1, D2, D3, D4 are not used
    • 
• ATCA introduction: http://www-ppd.fnal.gov/EEDOffice-w/Projects/ATCA/

• -- ZijunXu - 12 Apr 2014