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I Attachment History Action Size Date Who Comment
GIFgif ASIS_crate.gif r1 manage 323.5 K 2014-04-20 - 21:35 HangYin ASIS crate physical slots and logic slots number
PNGpng BottomLayer.PNG r1 manage 516.8 K 2015-05-25 - 06:04 ZijunXu  
Unknown file formatbit CPLL_example_ibert_44ch_fab_10gbps.bit r1 manage 28061.4 K 2014-06-06 - 15:52 ZijunXu  
Unknown file formatdocx Checklist.docx r1 manage 19.0 K 2016-06-23 - 21:20 ZijunXu Pulsar2b Checklist
PNGpng Clock_X1.PNG r1 manage 252.4 K 2014-04-19 - 00:58 ZijunXu  
PNGpng Clock_X2.PNG r1 manage 183.4 K 2014-04-19 - 00:58 ZijunXu  
PNGpng Clock_X5.PNG r1 manage 260.4 K 2014-04-19 - 00:58 ZijunXu  
SVG (Scalable Vector Graphics)svg ESD_Protected.svg r1 manage 2.1 K 2016-04-06 - 17:21 ZijunXu  
PNGpng FMC_IC.PNG r1 manage 28.8 K 2015-05-25 - 06:27 ZijunXu  
PNGpng FMC_Polarized_Cap.PNG r1 manage 659.8 K 2015-05-25 - 06:38 ZijunXu  
PNGpng FPGA_Done.png r1 manage 119.6 K 2014-04-26 - 07:22 ZijunXu  
PNGpng GND.PNG r1 manage 331.1 K 2014-04-18 - 22:25 ZijunXu  
PNGpng GTH_in_RTM.PNG r1 manage 183.6 K 2014-05-23 - 19:36 ZijunXu  
PDFpdf IBERT_for_PulsarIIb.pdf r1 manage 336.3 K 2014-06-06 - 16:13 ZijunXu  
Unknown file formatbin P2b_LEDBlinker.bin r1 manage 2583.6 K 2016-05-03 - 21:19 ZijunXu  
Unknown file formatbit PL2b_All20Quad_ref125_10Gbps.bit r1 manage 17387.2 K 2016-04-21 - 16:39 ZijunXu Pulsar2b IBERT vivado 2015p4p2
Unknown file formatbit PL2b_All20Quad_ref156p25_10p3125Gbps.bit r1 manage 17199.4 K 2016-04-21 - 16:38 ZijunXu Pulsar2b IBERT vivado 2015p4p2
Unknown file formatbit PL2b_All20Quad_ref200_10Gbps.bit r1 manage 17393.0 K 2016-04-21 - 16:42 ZijunXu  
Unknown file formatbit PL2b_Fab_All_ref125_10Gbps.bit r1 manage 9196.1 K 2016-04-21 - 02:11 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
Unknown file formatbit PL2b_Fab_Q113_ref125_10Gbps.bit r1 manage 4574.3 K 2016-04-21 - 02:12 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
Unknown file formatbit PL2b_Fab_Q113_ref156p25_10p3125Gbps.bit r1 manage 4708.4 K 2016-04-21 - 02:12 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
Unknown file formatbit PL2b_Fab_Q113_ref200_10Gbps.bit r1 manage 4640.7 K 2016-04-21 - 02:12 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
Unknown file formatbit PL2b_Fab_Q11567_ref125_10Gbps.bit r1 manage 5814.0 K 2016-04-21 - 02:12 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
PDFpdf Pulsar2B_testing.pdf r3 r2 r1 manage 3564.0 K 2014-05-27 - 18:40 ZijunXu  
Unknown file formatbit Pulsar2b_LEDBlinker.bit r1 manage 2583.7 K 2016-04-20 - 21:33 ZijunXu Pulsar2b_LEDBlinker vivado 2015p4p2
Unknown file formatbit QPLL_example_ibert_44ch_fab_10gbps.bit r1 manage 28061.5 K 2014-06-04 - 19:04 ZijunXu  
Unknown file formatbit QPLL_example_ibert_44ch_fab_8gbps.bit r1 manage 28061.4 K 2014-06-04 - 19:03 ZijunXu  
Unknown file formatbit QPLL_example_ibert_44ch_rtm_10gbps.bit r1 manage 28061.5 K 2014-06-04 - 19:08 ZijunXu  
Unknown file formatbit QPLL_example_ibert_44ch_rtm_8gbps.bit r1 manage 28061.4 K 2014-06-04 - 19:06 ZijunXu  
Unknown file formatbit QPLL_example_ibert_80ch_10gbps.bit r1 manage 28061.4 K 2014-06-06 - 15:54 ZijunXu  
PNGpng RTM2_GTHs.PNG r1 manage 160.9 K 2014-12-26 - 08:52 ZijunXu  
PNGpng RTM_v2p0.PNG r1 manage 280.2 K 2014-12-15 - 21:09 ZijunXu  
PNGpng RoutingTable.png r1 manage 205.6 K 2014-05-28 - 20:08 ZijunXu  
PNGpng TopLayer.PNG r1 manage 409.5 K 2015-05-25 - 06:05 ZijunXu  
PNGpng clock_setting.PNG r3 r2 r1 manage 237.4 K 2016-04-20 - 18:14 ZijunXu  
PNGpng clock_sw12.PNG r1 manage 273.7 K 2014-04-18 - 18:52 ZijunXu  
JPEGjpg crate_fullmesh.JPG r1 manage 2173.1 K 2014-05-27 - 18:34 ZijunXu  
Unknown file formatbit example_ibert_16ch_RTM_214_213_110_111_10.3125gbps_QPLL.bit r1 manage 28061.4 K 2014-06-30 - 22:54 ZijunXu  
Unknown file formatbit example_ibert_20ch_112_116_6gbps.bit r1 manage 28061.4 K 2014-04-29 - 16:55 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_24ch_210_213_110_111_6gbps.bit r1 manage 28061.4 K 2014-04-28 - 23:35 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, used for the RTM test with 24 activated channels (110, 111, 210 - 213), 6Gbps.
Unknown file formatbit example_ibert_24ch_213_218_6gbps.bit r1 manage 28061.4 K 2014-04-28 - 23:32 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, used for the RTM test with 24 activated channels (213 - 218), 6Gbps.
Unknown file formatbit example_ibert_44ch_fab_3gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:47 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_44ch_rtm_10gbps.bit r1 manage 28061.5 K 2014-04-24 - 17:38 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_44ch_rtm_3gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:42 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_44ch_rtm_6gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:40 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_44ch_rtm_8gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:39 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_4ch_116_10gbps.bit r1 manage 28061.4 K 2014-04-26 - 01:41 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_4ch_116_3gbps.bit r1 manage 28061.4 K 2014-04-26 - 01:44 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_4ch_116_6gbps.bit r1 manage 28061.5 K 2014-04-25 - 05:02 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_7series_11Quad_6p25G_ref125.bit r1 manage 28061.5 K 2014-11-24 - 21:01 ZijunXu  
Unknown file formatbit example_ibert_7series_11Quads_10Gbps_ref125.bit r1 manage 28061.5 K 2014-11-24 - 21:02 ZijunXu  
Unknown file formatbit example_ibert_7series_11Quads_8G_ref125.bit r1 manage 28061.5 K 2014-11-24 - 21:00 ZijunXu  
Unknown file formatbit example_ibert_7series_20Quads_10G_ref125.bit r1 manage 28061.5 K 2014-11-24 - 22:26 ZijunXu  
Unknown file formatbit example_ibert_7series_20Quads_10p3125_ref156.bit r1 manage 16898.6 K 2014-12-21 - 01:25 ZijunXu  
Unknown file formatbit example_ibert_7series_20Quads_6p25G_ref125.bit r1 manage 28061.5 K 2014-12-15 - 17:05 ZijunXu  
Unknown file formatbit example_ibert_7series_20Quads_8G_ref125.bit r1 manage 28061.5 K 2014-12-08 - 21:06 ZijunXu  
Unknown file formatbit example_ibert_80ch_10gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:56 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature.
Unknown file formatbit example_ibert_80ch_3gbps.bit r1 manage 28061.4 K 2014-04-24 - 18:00 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature.
Unknown file formatbit example_ibert_80ch_6gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:57 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature.
Unknown file formatbit example_ibert_80ch_8gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:59 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature.
Unknown file formatbit example_ibert_8ch_117_118_6gbps.bit r1 manage 28061.4 K 2014-04-28 - 23:30 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, used for the backplane test with 8 activated channels (117, 118), 6Gbps.
Unknown file formatbit example_ibert_bank_113.bit r1 manage 28061.4 K 2014-05-09 - 17:12 ZijunXu ibert firmware for VC709 bank 113, with 10.3125Gbps
Unknown file formatbit example_ibert_pulsarIIa_QPLL_allchannels_6p25Gbps.bit r1 manage 11175.5 K 2014-06-17 - 22:16 ZijunXu  
Unknown file formatbit example_ibert_pulsarIIa_allchannels_10Gbps.bit r1 manage 11175.5 K 2014-06-25 - 00:02 ZijunXu  
Unknown file formatbit example_ibert_pulsarIIa_allchannels_8Gbps.bit r2 r1 manage 11175.5 K 2014-06-25 - 01:05 ZijunXu  
Unknown file formatbit example_ibert_q118_10gbps.bit r1 manage 11175.5 K 2014-04-26 - 01:38 HangYin Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with different Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb.
Unknown file formatbit example_ibert_q118_3gbps.bit r1 manage 11175.5 K 2014-04-26 - 01:36 HangYin Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with 6 Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb.
Unknown file formatbit example_ibert_q118_6gbps.bit r1 manage 11175.5 K 2014-04-24 - 17:28 HangYin Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with 6 Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb.
Unknown file formatbit example_ibert_q118_8gbps.bit r1 manage 11175.5 K 2014-04-26 - 01:39 HangYin Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with different Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb.
Unknown file formatbit example_ibert_vertex7_gth_112_116_10gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:18 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_112_116_3gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:22 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_112_116_6gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:21 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_112_116_8gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:20 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_10gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:58 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_3gbps.bit r1 manage 28061.5 K 2014-04-24 - 19:03 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_3gbps_correct_clock.bit r1 manage 28061.5 K 2014-04-29 - 21:57 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_6gbps.bit r1 manage 28061.5 K 2014-04-24 - 19:01 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_8gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:59 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_pulsar2a_ibert_gtx12_10gbps.bit r1 manage 11175.6 K 2014-04-25 - 00:47 HangYin ISE only! For Pulsar IIa FPGA programming, with the external clock frequency, GTX12 activated.
Unknown file formatbit example_pulsar2a_ibert_gtx12_3gbps.bit r1 manage 11175.6 K 2014-04-25 - 00:49 HangYin ISE only! For Pulsar IIa FPGA programming, with the external clock frequency, GTX12 activated.
Unknown file formatbit example_pulsar2a_ibert_gtx12_6gbps.bit r1 manage 11175.6 K 2014-05-07 - 23:04 HangYin  
Unknown file formatbit example_pulsar2a_ibert_gtx12_8gbps.bit r1 manage 11175.6 K 2014-04-25 - 00:48 HangYin ISE only! For Pulsar IIa FPGA programming, with the external clock frequency, GTX12 activated.
PNGpng fuses.PNG r1 manage 425.1 K 2016-04-19 - 20:14 ZijunXu  
PNGpng jumper_fmc.png r2 r1 manage 213.8 K 2014-04-18 - 19:09 ZijunXu  
PNGpng jumper_fmc2.png r1 manage 3.9 K 2014-04-24 - 17:12 ZijunXu  
PNGpng jumper_zone1.png r2 r1 manage 268.4 K 2014-04-18 - 19:09 ZijunXu  
PNGpng jumper_zone3.png r2 r1 manage 367.1 K 2014-04-18 - 19:09 ZijunXu  
Unknown file formatbit main.bit r2 r1 manage 2640.6 K 2014-04-26 - 18:03 ZijunXu  
Unknown file formatbit mezz.bit r2 r1 manage 630.7 K 2014-04-26 - 18:03 ZijunXu  
PNGpng polarized_Capacitors.PNG r1 manage 318.2 K 2014-04-18 - 17:31 ZijunXu  
PNGpng polarized_Capacitors2.PNG r1 manage 295.8 K 2014-04-18 - 17:31 ZijunXu  
Unknown file formatgz pulsar2b_initial_test.tar.gz r1 manage 85.2 K 2014-04-25 - 08:33 HangYin framework
PNGpng refclock_assignment.png r1 manage 414.4 K 2014-04-26 - 22:44 ZijunXu  
PNGpng resistor_distri.PNG r1 manage 305.2 K 2014-05-25 - 00:53 ZijunXu  
PNGpng rtm_connector.png r2 r1 manage 101.2 K 2014-04-26 - 01:08 ZijunXu  
PNGpng rtm_power.png r2 r1 manage 159.0 K 2014-07-09 - 00:47 ZijunXu  
PNGpng rtm_power2.png r1 manage 11.8 K 2014-04-26 - 00:58 ZijunXu  
PNGpng valtage_12_U16.PNG r2 r1 manage 121.0 K 2014-05-27 - 18:07 ZijunXu  
PNGpng valtage_12_U171821.PNG r3 r2 r1 manage 207.7 K 2014-07-09 - 00:43 ZijunXu  
PNGpng valtage_12_U23.PNG r2 r1 manage 137.6 K 2014-05-27 - 18:17 ZijunXu  
PNGpng valtage_1_U17.PNG r1 manage 256.5 K 2014-04-18 - 23:25 ZijunXu  
PNGpng valtage_1_U21.PNG r1 manage 255.3 K 2014-04-18 - 23:28 ZijunXu  
PNGpng valtage_1p0_fpga.PNG r1 manage 293.3 K 2014-04-19 - 00:48 ZijunXu  
PNGpng valtage_1p2_U23.PNG r1 manage 190.6 K 2014-04-18 - 23:31 ZijunXu  
PNGpng valtage_1p5_U22.PNG r1 manage 211.6 K 2014-04-19 - 00:29 ZijunXu  
PNGpng valtage_1p5_fpga.PNG r1 manage 285.6 K 2014-04-19 - 00:27 ZijunXu  
PNGpng valtage_1p8_U18.PNG r1 manage 371.6 K 2014-04-18 - 23:54 ZijunXu  
PNGpng valtage_1p8_U29.PNG r1 manage 235.1 K 2014-04-19 - 00:37 ZijunXu  
PNGpng valtage_1p8_fpga.PNG r1 manage 289.8 K 2014-04-19 - 00:44 ZijunXu  
PNGpng valtage_3p3_U16.PNG r1 manage 267.0 K 2014-04-18 - 23:18 ZijunXu  
PNGpng valtage_pim3p3.PNG r2 r1 manage 104.0 K 2014-05-27 - 18:04 ZijunXu  
Unknown file formattcl vivado_fabric_scan.tcl r1 manage 4.3 K 2016-04-21 - 02:27 ZijunXu  
Unknown file formattcl vivado_fabric_setup.tcl r1 manage 7.6 K 2016-04-21 - 02:27 ZijunXu  
PNGpng voltage_summary.PNG r2 r1 manage 329.4 K 2014-04-24 - 18:01 ZijunXu  
JPEGjpg xilinx_FPGA.JPG r2 r1 manage 38.5 K 2016-07-14 - 21:31 ZijunXu from http://www.xilinx.com/support/documentation/errata/en206.pdf
Edit | Attach | Watch | Print version | History: r96 | r93 < r92 < r91 < r90 | Backlinks | View topic | Raw edit | More topic actions...
Topic revision: r91 - 2016-07-14 - ZijunXu
 
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