Completed Checklist for a new Pulsar IIb baord


Useful Information

Checklist for download: Checklist.docx, Checklist.pdf

Documentations

Anti-Static

ESD_Protected.svg

  • [ ] Before touching any boards/devices, using an anti-static wrist strap to keep your partner and yourself grounded;
  • [ ] When moving any boards/devices, using anti-static bags or boxes;

Visual Test

  • [ ] Pulsar2b is compatible with different types of xilinx Virtex-7 FPGA in the FFG1927 package:
    • [ ]XC7VX690T (80 GTX, default for CMS L1 Tracking Trigger project)
    • [ ]XC7VX550T (80 GTX);
    • [ ]XC7VX485T (56 GTX, Quads 113-119 & 213-219)
    • [ ]XC7VX415T (48 GTX, Quads 114-119 & 214-219)
    • xilinx_FPGA.JPG

  • [ ] Soldering quality: Solder joints should have a smooth appearance. A satin luster is permissible. The joints should be free from scratches, sharp edges, grittiness, looseness, blistering, or other evidence of poor workmanship. more details about soldering
  • [ ] *note: R72 and R80 should be empty
  • [ ] Orientation of IC's: see small ticks around the IC's;
  • [ ] all fuses are installed
    • F1, F2: 0.5A
    • F3, F4, F5, F6: 10A
    • fuses.PNG
  • [ ] polarity of capacitors:
    • polarized_Capacitors.PNGpolarized_Capacitors2.PNG
  • [ ] Measure the resistance value between 5 test points of GND. They should be 0~0.1 Ω.
    • GND.PNG
  • [ ] Measure the resistance value between power rails to GND
    • voltage_summary.PNG
    • The observed values could be different by 50% or more from reference value. It's safe if the observed value is larger than the reference value. But if the observed value is too small, please contract experts.
    • make sure the resistance value is far from 0. Be more careful about the VCC1V0.
Power Rails Referece Value(Ω)Sorted ascending Observed Value(Ω)
P5 MGTAVTT 1.2V 2.5K or 350  
P2 VCC3V3 3.0K  
P1 VCC12 3.5K  
P7 MGTAVCCAUX 1.8V 6.5K  
P3 VCC1V0 14.2  
P4 MGTAVCC 1.0V 111  
P8 VCC1V5 511  
P6 VCC1V8 650  
    • [ ] P1 VCC12 (from Power Converter U9): input for U16, U17, U18, U21, and U23;
    • valtage_12_U16.PNG
    • [ ] P2 VCC3V3: testing point (output of U16, 20A)
    • valtage_3p3_U16.PNG
    • [ ] P3 VCC1V0 testing point(VCCINT, CVVBRAM, output of U17, 40A)
    • valtage_1_U17.PNG
    • [ ] P4 MGTVACC : testing point (MGTVACC, output of U21, input of FPGA, 40A):
    • valtage_1_U21.PNG
    • [ ] P5 MGTAVTT :testing point (MGTAVTT, output of U23, 20A):
    • valtage_1p2_U23.PNG
    • [ ] P6 VCC1V8 : testing point (VCCAUX, VCCO, VCCAUX_IO, output of U18, input of FPGA, 6A)
    • valtage_1p8_U18.PNG
    • [ ] P7 MGTVCCAUX (MGTVCCAUX, output of U29, 3A)
    • valtage_1p8_U29.PNG
    • [ ] P8 VCC1V5 (VCCO, DDR3, output of U22, input of FPGA, 3A)
    • valtage_1p5_fpga.PNG

  • [ ] Measure these resistors for each Power Regulators :
    • U16: R22, R26, R28, R29;
    • U17: R23, R27, R30,R31;
    • U18: R24, R25, R32, R33;
    • U21: R34, R36, R38, R39;
    • U23: R35, R37, R40, R41.
    • All the resistor listed above are in the back of pulsarIIb board:
    • resistor_distri.PNG
    • (Note, the reference values are observed values from pulsarIIb board 3, as a reference.)
Regulator Resistor Schematic Value (Ω) Reference Value(Ω) Observed Value(Ω)
U16 R22 240 242  
R26 4.2k 4.19k  
R28 10k 10.05k  
R29 36.5k 36.2k  
U17 R23 240 242  
R27 30.0k 19.7k  
R30 23.7k 23.5k  
R31 23.7k 23.4k  
U18 R24 240 242  
R25 10k 8.88k  
R32 23.7k 23.5k  
R33 36.5k 36.4k  
U21 R34 240 242  
R36 30.0k 19.6k  
R38 36.5k 36.2k  
R39 23.7k 23.5k  
U23 R35 240 242  
R37 20.0k 15.8k  
R40 10k 10.05k  
R41 23.7k 23.5k  
  • [ ] Set Dip Switches (SW1,SW2) to 125MHz which is the default GTH reference clock frequence
    • Set the dip switches to 125 MHz configuration as default: {1, 1, 1, 1, 0, "X"} = {PR1, PR0, OD0, OD1, OD2, OPT}
    • Note: the "OPT" pin is not used to clock frequency configuration;
    • Note: both of the two switches are used for FPGA GTH reference clock;
    • Typical configuration are summerized below, more details please check the data sheet of CDCM61004;
    • clock_sw12.PNGclock_setting.PNG
  • [ ] Check the jumpers:
    • Zone 1 jumper (JP2):
      • OFF = IPMC CONTROL; ON = FORCE 12V ON;
      • When there is no IPMC, turn on to force 12V on;
      • jumper_zone1.png
    • 4 FMC jumpers (JP1-FMC1,2,3,4):
      • 1-2: BYPASS; 2-3: NORMAL;
      • when there is NO FMC mezzanine card, need to bypass this FMC connecter. 1 jumper as example:
      • jumper_fmc.pngjumper_fmc2.png
    • Zone3 jumpers (JP3, JP4):
      • ON = IPMC CONTROL; OFF = FORCE ON; (opposite to Zone1 jumper JP2)
      • when there is no IPMC, OFF to force RTM power on:
      • jumper_zone3.png
  • [ ] Installing a proper heat sink to the Pulsar2b FPGA, and preparing a fan for cooling;

Voltages Test

  • [ ] Use anti-static wrist strap to ground yourself.
  • [ ] Using the 1U ATCA crate for testing. (if you only have a mini-backplane for testing, then, setup the mini backplan with proper voltage applied.(recommend 48V , can work from 36V to 72V, ) )
  • [ ] Turn on the fan for cooling.

    Initial configuration for the first testing:
  • [ ] No IPMC
  • [ ] No RTM;
  • [ ] No FMC, so JP1-FMC1,2,3,4 set to bypass(connect 1-2);

    At first, testing the management voltage:
  • [ ] Without IPMC mezzanine card, but turn JP2 off, so the 12V voltage are off, while the management voltage (3.3V from PIM) still on:
  • valtage_pim3p3.PNG
  • [ ] After this test, turn off the main voltage.
  • [ ] Check all jumpers' pin status again.
    • [ ] without IPMC mezzanine card, JP2 ON, JP3 OFF, JP4 OFF;
  • [ ] Turn on the main voltage.
    • Note: immediately 12V will be on and all the voltage will be activated;
    • Note: hot swap handle do not work without IPMC card. Turning off the main voltage will directly turn off the pulsar2b board.
  • [ ] Check current value (before FPGA is programmed);
  • [ ] Probe voltage of several points to check if they are expected:
    • [ ] 5 test points of GND:
    • GND.PNG
    • Note: Summary of positions of power regulators:
    • voltage_summary.PNG
    • Note: the difference between observed value and expected value should be less than 0.5%
Power Rails Observed Voltage(V)
P1 VCC12  
P2 VCC3V3  
P3 VCC1V0  
P4 MGTAVCC 1.0V  
P5 MGTAVTT 1.2V  
P6 VCC1V8  
P7 MGTAVCCAUX 1.8V  
P8 VCC1V5  
RTM (12V)  

    • [ ] VCC12 (from Power Converter U9): input for U16, U17, U18, U21, and U23;
      • U16: C103, C104
      • valtage_12_U16.PNG
      • U17: C115, C117, and C118; U18: C110 and C111; U21: C107 and C108;
      • valtage_12_U171821.PNG
      • U23: C119, C121,and C122;
      • valtage_12_U23.PNG
    • [ ] VCC3V3: testing point (output of U16, 20A)
    • valtage_3p3_U16.PNG
    • [ ] VCC1V0 testing point(VCCINT, CVVBRAM, output of U17, 40A)
    • valtage_1_U17.PNG
    • [ ] VCC1V0 : testing point (MGTVACC, output of U21, input of FPGA, 40A):
    • valtage_1_U21.PNGvaltage_1p0_fpga.PNG
    • [ ] VCC1V2 :testing point (MGTATT, output of U23, 20A):
    • valtage_1p2_U23.PNG
    • [ ] VCC1V8 : testing point (VCCAUX, VCCO, VCCAUX_IO, output of U18, input of FPGA, 6A)
    • valtage_1p8_U18.PNGvaltage_1p8_fpga.PNG
    • [ ] VCC1V5 (VCCO, DDR3, output of U22, input of FPGA, 3A)
    • valtage_1p5_fpga.PNG
    • [ ] VCC1V8 (MGTVCCAUX, output of U29, 3A)
    • Note: this pin should be probed, be careful not to have short circuit!!)
    • valtage_1p8_U29.PNG
    • [ ] Probe the power output from Pulsar IIb board zone-3:
      • 12V at D10, which is a schottky rectifier
      • rtm_power.png

First LED Blinking Test

  • [ ] Check 4 FMC jumpers( JP1-FMC1,2,3,4) connection before JTAG programming: if there is no FMC card, to connect 1-2 to bypass this FMC connector.
  • [ ] Programming FPGA with the LED blinker firmware: Pulsar2b_LEDBlinker.bit:
    • [ ] Check the DONE LED( D1): Blue color
      • FPGA_Done.png
    • [ ] Take care for temperature when you program new firmware ALWAYS (SET 75C^o as up limit).
    • [ ] There are four LEDs in frond panel, if input clock frequency is A MHz, for example 200 MHz:
      • 1st LED : A*1e6/2^(25+1) = 2.98 Hz
      • 2nd LED: A*1e6/2^(26+1) = 1.49 Hz
      • 3rd LED : A*1e6/2^(27+1) =0.745 Hz
      • 4th LED : A*1e6/2^(28+1) =0.373 Hz
  • [ ] store the firmware into SPI memory

IBERT Test

clock_setting.PNG

Set the reference clock to 125MHz, GTH speed is 10.0Gbps

[ ] 4 GTHs (Quad-113) at 10Gbps: PL2b_Fab_Q113_ref125_10Gbps.bit

[ ] 12 GTHs ( Quad-115,116,117) at 10Gbps: PL2b_Fab_Q11567_ref125_10Gbps.bit

[ ] 32 GTHs ( Quad-111 to Quad-118) at 10Gbps: PL2b_Fab_All_ref125_10Gbps.bit. All the 28 channels for Fabric Interface could be test by this firmware;

[ ] 80 GTHs ( Quad-210 to Quad-219, and Quad-110 to Quad-119) at 10Gbps: PL2b_All20Quad_ref125_10Gbps.bit. All the 80 GTHs could be test by this firmware;

Vivado TCL scripts for testing fabric interface: vivado_fabric_setup.tcl, vivado_fabric_scan.tcl;

for FMC loopback: vivado_FMCLoop_setup.tcl, vivado_FMCLoop_scan.tcl;

for RTM test: vivado_rtms_setup.tcl, vivado_rtms_scan.tcl

Set the reference clock to 200MHz, GTH speed is 10.0Gbps

[ ] 4 GTHs( Quad-113) at 10Gbps: PL2b_Fab_Q113_ref200_10Gbps.bit;

[ ] 80 GTHs ( Quad-210 to Quad-219, and Quad-110 to Quad-119) at 10Gbps: PL2b_All20Quad_ref200_10Gbps.bit

Set the reference clock to 156.25MHZ, GTH speed is 10.3125Gbps

[ ] 4 GTHs( Quad-113) at 10.3125Gbps: PL2b_Fab_Q113_ref156p25_10p3125Gbps.bit

[ ] 80 GTHs ( Quad-210 to Quad-219, and Quad-110 to Quad-119) at 10Gbps: PL2b_All20Quad_ref156p25_10p3125Gbps.bit

Note1: 28 GTHs used for Fabric: Quad-111-2 to Quad-118-1 (or X1Y6 to X1Y33)

Note2: 12(=3x4) GTHs used for FMC cards (1 to 4) are: [219-3,219-2,219-1], [219-0, 218-3,218-2], [118-2,118-3,119-0], [119-1,119-2,119-3]; (or [X0Y39 to X0Y37 ], [X0Y36 to X0Y34 ], [X1Y34 to X1Y36 ], [X1Y37 to X1Y39 ])

Note3: The rest 40 GTHs used for RTM;

RTM2_GTHs.PNG

FMC LVDS

Firmware for testing the FMC lvds channels with FMC loopback cards:

PL2b_LVDS_loopback_BERT_100MHz_FMC1.bit,

PL2b_LVDS_loopback_BERT_100MHz_FMC2.bit,

PL2b_LVDS_loopback_BERT_100MHz_FMC3.bit,

PL2b_LVDS_loopback_BERT_100MHz_FMC4.bit,

and PL2b_LVDS_loopback_BERT.ltx.

Appendix

Introduction of how to use vivado to do ibert testing: link

8 Reference Clock assignment for GTH:

RefClk 0 MGTREFCLK0_118
RefClk 1 MGTREFCLK0_115
RefClk 2 MGTREFCLK0_219
RefClk 3 MGTREFCLK0_112
RefClk 4 MGTREFCLK0_110
RefClk 5 MGTREFCLK0_211
RefClk 6 MGTREFCLK0_214
RefClk 7 MGTREFCLK0_217
refclock_assignment.png

Below is a summary of which Reference Clock could be used for each GTH

GTH Ref Clk
210 MGTREFCLK0_211
211 MGTREFCLK0_211
212 MGTREFCLK0_211
213 MGTREFCLK0_214
214 MGTREFCLK0_214
215 MGTREFCLK0_214
216 MGTREFCLK0_217
217 MGTREFCLK0_217
218 MGTREFCLK0_217, 219
219 MGTREFCLK0_219
   
110 MGTREFCLK0_110
111 MGTREFCLK0_110, 112
112 MGTREFCLK0_112
113 MGTREFCLK0_112
114 MGTREFCLK0_115
115 MGTREFCLK0_115
116 MGTREFCLK0_115
117 MGTREFCLK0_118
118 MGTREFCLK0_118
119 MGTREFCLK0_118
Below is GTHs assignments of the old version RTM, which was mounted with QSFP+ and SFP+ modules. (213-2 and 111-1 are not connected)

GTH_in_RTM.PNG

Below is the RTM v2.0 GTHs assignments:

RTM2_GTHs.PNG

28 GTHs used for Fabric: GTX111-2 to GTX118-1. In new mini-backplane, GTX118-1 is connected to SFP+ connector, other are looped back.

12(=3x4) GTHs used for FMC cards(1 to 4) are: [219-3,219-2,219-1], [219-0, 218-3,218-2], [118-2,118-3,119-0], [119-1,119-2,119-3];

Summary of the GTH channals have been reversed: ("R"=reversed, "-" = normal )

GTH TX RX
GTX211_2 (RTM) R -
GTX212_2 (RTM) - R
GTX212_3 (RTM) R -
GTX214_0 (RTM) - R
GTX218_3 (FMC) R -
GTX219_1 (FMC) - R
GTX219_2 (FMC) - R
GTX219_3 (FMC) R R
     
GTX110_0 (RTM) R R
GTX110_1 (RTM) R R
GTX110_2 (RTM) R R
GTX110_3 (RTM) R R
GTX111_0 (RTM) R -
GTX111_2 (fab) R -
GTX114_3 (fab) - R
GTX118_2 (FMC) - R
GTX119_1 (FMC) R R
GTX119_2 (FMC) R -
GTX119_3 (FMC) - R
FPGA IBERT testing start:
  • [ ] Make sure the clock frequency is setting to 200 MHZ for both Pulsar IIa and Pulsar IIb boards
  • [ ] Note: start from mini-backplane with good cooling;
  • [ ] Note: start from small number of GTHs and low speed (6Gbps as start point);
  • [ ] Note: check current and temperature when increasing number of GTH;
  • [ ] Check the functionality with internal LOOP back (to check functionality firmware programming / clock distribution etc)
  • [ ] Check the functionality with external LOOP back with as many pattern as possible
    • NOTE : step-by-step from single FPGA standalone, loop back at the other FPGA (so-called far-end Loop back mentioned in Figure 2-26 of UG476) with two board
  • [ ] Check the error rate (~ E-014, 20 mins running) and 2-D eye diagrams for each channels
  • [ ] IBERT firmwares

IBERT firmwares with GTH refrence CLK=200MHz
Pulsar Vidado (Y/N) # of channels Channels Usage Speed (Gbps) Speed (Gbps) Speed (Gbps) Speed (Gbps)
IIb Y 4 with CPLL 116 Fabric [ 3] [ 6] [ 8] [ 10]
IIb Y 8 with CPLL 117, 118 Fabric 3 [ 6] 8 10
IIb Y 20 with CPL 112 - 116 Fabric 3 [ 6] 8 10
IIb Y 24 with CPLL 213 - 218 RTM 3 [ 6] 8 10
IIb Y 24 with CPLL 110, 111, 210 - 213 RTM 3 [ 6] 8 10
IIb Y 44 with CPLL 111 - 119, 218, 219 Fabric [ 3]     [ 10]
IIb Y 44 with QPLL 111 - 119, 218, 219 Fabric     [ 8] [ 10]
IIb Y 44 with CPLL 110, 111, 210 - 218 RTM [ 3] [ 6] [ 8] [ 10]
IIb y 44 with QPLL 110, 111, 210 - 218 RTM     [ 8] [ 10]
IIb Y 80 with CPLL   All [ 3] [ 6] [ 8] [ 10]
IIb Y 80 with QPLL   All       [ 10]
IIb N 20 with CPLL 112 - 116 Fabric [ 3] [ 6] [ 8] [ 10]
IIa N 1 with CPLL GTX12 Fabric [ 3] [ 6] [ 8] [ 10]
IIa Y( only work in Vivado) 4 with CPLL GTX12 - GTX15 Fabric [ 3] [ 6] [ 8] [ 10]
IBERT firmwares with GTH refrence CLK=125MHz
Pulsar Vidado (Y/N) # of channels Channels Usage Speed (Gbps) Speed (Gbps) Speed (Gbps) Speed (Gbps)
IIb Y 44 with QPLL 111 - 119, 218, 219 Fabric   [ 6.25] [ 8] [ 10] [ 10.3125 with refclk156]
IIb Y 80 with QPLL   All   [ 6.25] [ 8] [ 10]
Vivado + Pulsar IIa firmware [ details] Vivado + Pulsar IIb firmware details]

Could connect RTM with Vertex 7 Evaluation kit, so we can seperate Tx and Rx effects. vc709 firmware for bank113: 10.3125 Gbps, PulsarIIb firmware for RTM SFP+ channels: 10.3125 Gbps

ps: please change pulsarIIb SW1 and SW2 to 156.25MHz.

PulsarIIa 6.25 Gbps firmware , 8Gbps firmware, and 10Gbps firmware from ISE with SYSCLK=200MHz, RefCLK =125MHZ.

Note:

1) introduction of making IBERT farmware for PulsarIIb : here

GTX LOOP back test

  • [ ] RTM QSFP+, SFP+ loopback test . GTX110_0 to GTX111_1, and GTX210_0 to GTX218_1
  • [ ] Fabric backplane test: to be developed. GTX111_2 to GTX118_1

FMC (FPGA Mezzanine card) v2.0 test

More details is here: Link

  • [ ] Clock forwarding test: from pulsar2b main FPGA to mezzanine card FPGA;
    • Program Pulsar IIb FPGA with [ firmware]; (btw, this firmware is same one of the LED blinking test.)
    • Program mezzanine card FPGA with [ firmware].

Insertion to ATCA shelf

You can find the connection channel between any two slots in below table:

RoutingTable.png

logical ( physical* ) Slot# 1 (7) 2 (8) 3 (6) 4 (9) 5 (5) 6 (10) 7 (4) 8 (11) 9 (3) 10 (12) 11 (2) 12 (13) 13 (1) 14 (14)
1 (7)  

117-2,-3,

118-0,-1

118-0,-1 118-0,-1 118-0,-1 118-0,-1 118-0,-1 118-0,-1 118-0,-1 118-0,-1 118-0,-1 118-0,-1 118-0,-1 118-0,-1
2 (8) 117-2,-3,118-0,-1   117-0,-1 117-0,-1 117-0,-1 117-0,-1 117-0,-1 117-0,-1 117-0,-1 117-0,-1 117-0,-1 117-0,-1 117-0,-1 117-0,-1
3 (6) 117-0,-1 117-0,-1   116-2,-3 116-2,-3 116-2,-3 116-2,-3 116-2,-3 116-2,-3 116-2,-3 116-2,-3 116-2,-3 116-2,-3 116-2,-3
4 (9) 116-2,-3 116-2,-3 116-2,-3   116-0,-1 116-0,-1 116-0,-1 116-0,-1 116-0,-1 116-0,-1 116-0,-1 116-0,-1 116-0,-1 116-0,-1
5 (5) 116-0,-1 116-0,-1 116-0,-1 116-0,-1   115-2,-3 115-2,-3 115-2,-3 115-2,-3 115-2,-3 115-2,-3 115-2,-3 115-2,-3 115-2,-3
6 (10) 115-2,-3 115-2,-3 115-2,-3 115-2,-3 115-2,-3   115-0,-1 115-0,-1 115-0,-1 115-0,-1 115-0,-1 115-0,-1 115-0,-1 115-0,-1
7 (4) 115-0,-1 115-0,-1 115-0,-1 115-0,-1 115-0,-1 115-0,-1   114-2,-3 114-2,-3 114-2,-3 114-2,-3 114-2,-3 114-2,-3 114-2,-3
8 (11) 114-2,-3 114-2,-3 114-2,-3 114-2,-3 114-2,-3 114-2,-3 114-2,-3   114-0,-1 114-0,-1 114-0,-1 114-0,-1 114-0,-1 114-0,-1
9 (3) 114-0,-1 114-0,-1 114-0,-1 114-0,-1 114-0,-1 114-0,-1 114-0,-1 114-0,-1   113-2,-3 113-2,-3 113-2,-3 113-2,-3 113-2,-3
10 (12) 113-2,-3 113-2,-3 113-2,-3 113-2,-3 113-2,-3 113-2,-3 113-2,-3 113-2,-3 113-2,-3   113-0,-1 113-0,-1 113-0,-1 113-0,-1
11 (2) 113-0,-1 113-0,-1 113-0,-1 113-0,-1 113-0,-1 113-0,-1 113-0,-1 113-0,-1 113-0,-1 113-0,-1   112-2,-3 112-2,-3 112-2,-3
12 (13) 112-2,-3 112-2,-3 112-2,-3 112-2,-3 112-2,-3 112-2,-3 112-2,-3 112-2,-3 112-2,-3 112-2,-3 112-2,-3   112-0,-1 112-0,-1
13 (1) 112-0,-1 112-0,-1 112-0,-1 112-0,-1 112-0,-1 112-0,-1 112-0,-1 112-0,-1 112-0,-1 112-0,-1 112-0,-1 112-0,-1   111-2,-3
14 (14) 111-2,-3 111-2,-3 111-2,-3 111-2,-3 111-2,-3 111-2,-3 111-2,-3 111-2,-3 111-2,-3 111-2,-3 111-2,-3 111-2,-3 111-2,-3  
In this table, the logical slot# in column is RX(receiver), and slot# in row is TX(transmitter). and like "116-0,-1" denots " 116-0 and 116-1".

* the mapping between physical number and logical number is depending on the shelf design. For same logical slot number, different shelfs may have different physical number.

Quad_210: MGT_X0Y0, X0Y1, X0Y2, X0Y3

Quad_211: MGT_X0Y4, X0Y5, X0Y6, X0Y7

Quad_212: MGT_X0Y8, X0Y9, X0Y10, X0Y11

Quad_213: MGT_X0Y12, X0Y12, X0Y14, X0Y15

Quad_214: MGT_X0Y16, X0Y17, X0Y18, X0Y19

Quad_215: MGT_X0Y20, X0Y21, X0Y22, X0Y23

Quad_216: MGT_X0Y24, X0Y25, X0Y26, X0Y27

Quad_217: MGT_X0Y28, X0Y29, X0Y30, X0Y31

Quad_218: MGT_X0Y32, X0Y33, X0Y34, X0Y35

Quad_219: MGT_X0Y36, X0Y37, X0Y38, X0Y39

Quad_110: MGT_X1Y0, X1Y1, X1Y2, X1Y3

Quad_111: MGT_X1Y4, X1Y5, X1Y6, X1Y7

Quad_112: MGT_X1Y8, X1Y9, X1Y10, X1Y11

Quad_113: MGT_X1Y12, X1Y13, X1Y14, X1Y15

Quad_114: MGT_X1Y16, X1Y17, X1Y18, X1Y19

Quad_115: MGT_X1Y20, X1Y21, X1Y22, X1Y23

Quad_116: MGT_X1Y24, X1Y25, X1Y26, X1Y27

Quad_117: MGT_X1Y28, X1Y29, X1Y30, X1Y31

Quad_118: MGT_X1Y32, X1Y33, X1Y34, X1Y35

Quad_119: MGT_X1Y36, X1Y37, X1Y38, X1Y39

  • [ ] This step must after comfirmation with minibackplane.
  • [ ] First is to test one board with internel loopback; Then to do the combined test with pulsar2a;
  • [ ] Take the other baord off, and put the new board to ATCA and turn on: Pulsar IIa and Pulsar IIb in Slot-3 and Slot-4
    • ASIS_crate.gif

  • [ ] Program Pulsar IIa board with MGT12 [ bit file], for both top and bottom FPGAs.
  • [ ] Program Pulsar IIb board with GTH116 [ bit file]
  • [ ] Access to the FPGA through the ChipScope use the GUI, check the links between FPGAs
  • [ ] Check Fabric Interface, Base Interface, Management Interface etc.

  • [ ] Clock probing points::
    • SYSCLOCK (X5), 200 MHz (5ns period);
    • Clock_X5.PNG
    • crystal oscillator (25MHz) {X1, X2};
    • Clock_X1.PNG Clock_X2.PNG

RTM Power Test

  • [ ] Probe the power output from Pulsar IIb board zone-3:
    • 12V at D10, which is a schottky rectifier
    • rtm_power.png
    • 12V power and 3.3V manage power inside the blue connector:
      • Only probe the orange pins, not touch the black pins;
          • A1: 0V. It's Manage Power, only when RTM connected, it's 3.3V;
          • A2: GND;
          • A3: 12V;
          • A4: GND;
          • B2: 3.3V(PNs) when RTM is disconnected;
          • B3: 12V;
          • B4: GND
      • black pins:
          • B1: ENABLEn
          • C1: SCL_L
          • C2: SDA_L
          • C3, C4, D1, D2, D3, D4 are not used
      • rtm_connector.pngrtm_power2.png
  • ATCA introduction: http://www-ppd.fnal.gov/EEDOffice-w/Projects/ATCA/
  • -- ZijunXu - 12 Apr 2014
Topic attachments
I Attachment History Action Size Date Who Comment
GIFgif ASIS_crate.gif r1 manage 323.5 K 2014-04-20 - 21:35 HangYin ASIS crate physical slots and logic slots number
PNGpng BottomLayer.PNG r1 manage 516.8 K 2015-05-25 - 06:04 ZijunXu  
Unknown file formatbit CPLL_example_ibert_44ch_fab_10gbps.bit r1 manage 28061.4 K 2014-06-06 - 15:52 ZijunXu  
Unknown file formatdocx Checklist.docx r2 r1 manage 23.2 K 2016-08-17 - 16:41 ZijunXu Pulsar2b Checklist
PDFpdf Checklist.pdf r1 manage 435.5 K 2016-08-17 - 16:42 ZijunXu  
PNGpng Clock_X1.PNG r1 manage 252.4 K 2014-04-19 - 00:58 ZijunXu  
PNGpng Clock_X2.PNG r1 manage 183.4 K 2014-04-19 - 00:58 ZijunXu  
PNGpng Clock_X5.PNG r1 manage 260.4 K 2014-04-19 - 00:58 ZijunXu  
SVG (Scalable Vector Graphics)svg ESD_Protected.svg r1 manage 2.1 K 2016-04-06 - 17:21 ZijunXu  
PNGpng FMC_IC.PNG r1 manage 28.8 K 2015-05-25 - 06:27 ZijunXu  
PNGpng FMC_Polarized_Cap.PNG r1 manage 659.8 K 2015-05-25 - 06:38 ZijunXu  
PNGpng FPGA_Done.png r1 manage 119.6 K 2014-04-26 - 07:22 ZijunXu  
PNGpng GND.PNG r1 manage 331.1 K 2014-04-18 - 22:25 ZijunXu  
PNGpng GTH_in_RTM.PNG r1 manage 183.6 K 2014-05-23 - 19:36 ZijunXu  
PDFpdf IBERT_for_PulsarIIb.pdf r1 manage 336.3 K 2014-06-06 - 16:13 ZijunXu  
Unknown file formatbin P2b_LEDBlinker.bin r1 manage 2583.6 K 2016-05-03 - 21:19 ZijunXu  
Unknown file formatbit PL2b_All20Quad_ref125_10Gbps.bit r1 manage 17387.2 K 2016-04-21 - 16:39 ZijunXu Pulsar2b IBERT vivado 2015p4p2
Unknown file formatbit PL2b_All20Quad_ref156p25_10p3125Gbps.bit r1 manage 17199.4 K 2016-04-21 - 16:38 ZijunXu Pulsar2b IBERT vivado 2015p4p2
Unknown file formatbit PL2b_All20Quad_ref200_10Gbps.bit r1 manage 17393.0 K 2016-04-21 - 16:42 ZijunXu  
Unknown file formatbit PL2b_Fab_All_ref125_10Gbps.bit r1 manage 9196.1 K 2016-04-21 - 02:11 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
Unknown file formatbit PL2b_Fab_Q113_ref125_10Gbps.bit r1 manage 4574.3 K 2016-04-21 - 02:12 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
Unknown file formatbit PL2b_Fab_Q113_ref156p25_10p3125Gbps.bit r1 manage 4708.4 K 2016-04-21 - 02:12 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
Unknown file formatbit PL2b_Fab_Q113_ref200_10Gbps.bit r1 manage 4640.7 K 2016-04-21 - 02:12 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
Unknown file formatbit PL2b_Fab_Q11567_ref125_10Gbps.bit r1 manage 5814.0 K 2016-04-21 - 02:12 ZijunXu Pulsar2b IBERT by vivado 2015p4p2
Unknown file formatltx PL2b_LVDS_loopback_BERT.ltx r1 manage 13.0 K 2016-07-14 - 23:01 ZijunXu  
Unknown file formatbit PL2b_LVDS_loopback_BERT_100MHz_FMC1.bit r1 manage 3094.3 K 2016-07-14 - 23:01 ZijunXu  
Unknown file formatbit PL2b_LVDS_loopback_BERT_100MHz_FMC2.bit r1 manage 2959.2 K 2016-07-14 - 23:01 ZijunXu  
Unknown file formatbit PL2b_LVDS_loopback_BERT_100MHz_FMC3.bit r1 manage 3094.0 K 2016-07-14 - 23:01 ZijunXu  
Unknown file formatbit PL2b_LVDS_loopback_BERT_100MHz_FMC4.bit r1 manage 3078.2 K 2016-07-14 - 23:01 ZijunXu  
PDFpdf Pulsar2B_testing.pdf r3 r2 r1 manage 3564.0 K 2014-05-27 - 18:40 ZijunXu  
Unknown file formatbit Pulsar2b_LEDBlinker.bit r1 manage 2583.7 K 2016-04-20 - 21:33 ZijunXu Pulsar2b_LEDBlinker vivado 2015p4p2
Unknown file formatbit QPLL_example_ibert_44ch_fab_10gbps.bit r1 manage 28061.5 K 2014-06-04 - 19:04 ZijunXu  
Unknown file formatbit QPLL_example_ibert_44ch_fab_8gbps.bit r1 manage 28061.4 K 2014-06-04 - 19:03 ZijunXu  
Unknown file formatbit QPLL_example_ibert_44ch_rtm_10gbps.bit r1 manage 28061.5 K 2014-06-04 - 19:08 ZijunXu  
Unknown file formatbit QPLL_example_ibert_44ch_rtm_8gbps.bit r1 manage 28061.4 K 2014-06-04 - 19:06 ZijunXu  
Unknown file formatbit QPLL_example_ibert_80ch_10gbps.bit r1 manage 28061.4 K 2014-06-06 - 15:54 ZijunXu  
PNGpng RTM2_GTHs.PNG r1 manage 160.9 K 2014-12-26 - 08:52 ZijunXu  
PNGpng RTM_v2p0.PNG r1 manage 280.2 K 2014-12-15 - 21:09 ZijunXu  
PNGpng RoutingTable.png r1 manage 205.6 K 2014-05-28 - 20:08 ZijunXu  
PNGpng TopLayer.PNG r1 manage 409.5 K 2015-05-25 - 06:05 ZijunXu  
PNGpng clock_setting.PNG r3 r2 r1 manage 237.4 K 2016-04-20 - 18:14 ZijunXu  
PNGpng clock_sw12.PNG r1 manage 273.7 K 2014-04-18 - 18:52 ZijunXu  
JPEGjpg crate_fullmesh.JPG r1 manage 2173.1 K 2014-05-27 - 18:34 ZijunXu  
Unknown file formatbit example_ibert_16ch_RTM_214_213_110_111_10.3125gbps_QPLL.bit r1 manage 28061.4 K 2014-06-30 - 22:54 ZijunXu  
Unknown file formatbit example_ibert_20ch_112_116_6gbps.bit r1 manage 28061.4 K 2014-04-29 - 16:55 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_24ch_210_213_110_111_6gbps.bit r1 manage 28061.4 K 2014-04-28 - 23:35 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, used for the RTM test with 24 activated channels (110, 111, 210 - 213), 6Gbps.
Unknown file formatbit example_ibert_24ch_213_218_6gbps.bit r1 manage 28061.4 K 2014-04-28 - 23:32 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, used for the RTM test with 24 activated channels (213 - 218), 6Gbps.
Unknown file formatbit example_ibert_44ch_fab_3gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:47 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_44ch_rtm_10gbps.bit r1 manage 28061.5 K 2014-04-24 - 17:38 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_44ch_rtm_3gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:42 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_44ch_rtm_6gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:40 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_44ch_rtm_8gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:39 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. For the files named "fab", means backplane fabric connections and FMC connections, with 44 activated channels (111-119, 218 and 219); for the files named with "rtm", mainly used for RTM testing, with 44 activated channels (110, 111, 210 - 218).
Unknown file formatbit example_ibert_4ch_116_10gbps.bit r1 manage 28061.4 K 2014-04-26 - 01:41 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_4ch_116_3gbps.bit r1 manage 28061.4 K 2014-04-26 - 01:44 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_4ch_116_6gbps.bit r1 manage 28061.5 K 2014-04-25 - 05:02 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_7series_11Quad_6p25G_ref125.bit r1 manage 28061.5 K 2014-11-24 - 21:01 ZijunXu  
Unknown file formatbit example_ibert_7series_11Quads_10Gbps_ref125.bit r1 manage 28061.5 K 2014-11-24 - 21:02 ZijunXu  
Unknown file formatbit example_ibert_7series_11Quads_8G_ref125.bit r1 manage 28061.5 K 2014-11-24 - 21:00 ZijunXu  
Unknown file formatbit example_ibert_7series_20Quads_10G_ref125.bit r1 manage 28061.5 K 2014-11-24 - 22:26 ZijunXu  
Unknown file formatbit example_ibert_7series_20Quads_10p3125_ref156.bit r1 manage 16898.6 K 2014-12-21 - 01:25 ZijunXu  
Unknown file formatbit example_ibert_7series_20Quads_6p25G_ref125.bit r1 manage 28061.5 K 2014-12-15 - 17:05 ZijunXu  
Unknown file formatbit example_ibert_7series_20Quads_8G_ref125.bit r1 manage 28061.5 K 2014-12-08 - 21:06 ZijunXu  
Unknown file formatbit example_ibert_80ch_10gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:56 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature.
Unknown file formatbit example_ibert_80ch_3gbps.bit r1 manage 28061.4 K 2014-04-24 - 18:00 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature.
Unknown file formatbit example_ibert_80ch_6gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:57 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature.
Unknown file formatbit example_ibert_80ch_8gbps.bit r1 manage 28061.4 K 2014-04-24 - 17:59 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ. With entire 80 activated channels, and different speeds. Be careful about the FPGA temperature.
Unknown file formatbit example_ibert_8ch_117_118_6gbps.bit r1 manage 28061.4 K 2014-04-28 - 23:30 HangYin Vivado only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, used for the backplane test with 8 activated channels (117, 118), 6Gbps.
Unknown file formatbit example_ibert_bank_113.bit r1 manage 28061.4 K 2014-05-09 - 17:12 ZijunXu ibert firmware for VC709 bank 113, with 10.3125Gbps
Unknown file formatbit example_ibert_pulsarIIa_QPLL_allchannels_6p25Gbps.bit r1 manage 11175.5 K 2014-06-17 - 22:16 ZijunXu  
Unknown file formatbit example_ibert_pulsarIIa_allchannels_10Gbps.bit r1 manage 11175.5 K 2014-06-25 - 00:02 ZijunXu  
Unknown file formatbit example_ibert_pulsarIIa_allchannels_8Gbps.bit r2 r1 manage 11175.5 K 2014-06-25 - 01:05 ZijunXu  
Unknown file formatbit example_ibert_q118_10gbps.bit r1 manage 11175.5 K 2014-04-26 - 01:38 HangYin Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with different Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb.
Unknown file formatbit example_ibert_q118_3gbps.bit r1 manage 11175.5 K 2014-04-26 - 01:36 HangYin Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with 6 Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb.
Unknown file formatbit example_ibert_q118_6gbps.bit r1 manage 11175.5 K 2014-04-24 - 17:28 HangYin Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with 6 Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb.
Unknown file formatbit example_ibert_q118_8gbps.bit r1 manage 11175.5 K 2014-04-26 - 01:39 HangYin Vivado only! This is the bit file for MGT12, MGT 13, MGT14, and MGT15 at Pulsar IIa, with different Gbps speed, external clock 200 MHZ, and to be used for the first initial test between Pulsar IIa and Pulsar IIb.
Unknown file formatbit example_ibert_vertex7_gth_112_116_10gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:18 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_112_116_3gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:22 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_112_116_6gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:21 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_112_116_8gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:20 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 20 channels from GTH 112 to GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_10gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:58 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_3gbps.bit r1 manage 28061.5 K 2014-04-24 - 19:03 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_3gbps_correct_clock.bit r1 manage 28061.5 K 2014-04-29 - 21:57 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_6gbps.bit r1 manage 28061.5 K 2014-04-24 - 19:01 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_ibert_vertex7_gth_116_8gbps.bit r1 manage 28061.5 K 2014-04-24 - 18:59 HangYin ISE only! For Pulsar IIb FPGA programming, with the external clock frequency of 200 MHZ, activated 4 channels for GTH 116.
Unknown file formatbit example_pulsar2a_ibert_gtx12_10gbps.bit r1 manage 11175.6 K 2014-04-25 - 00:47 HangYin ISE only! For Pulsar IIa FPGA programming, with the external clock frequency, GTX12 activated.
Unknown file formatbit example_pulsar2a_ibert_gtx12_3gbps.bit r1 manage 11175.6 K 2014-04-25 - 00:49 HangYin ISE only! For Pulsar IIa FPGA programming, with the external clock frequency, GTX12 activated.
Unknown file formatbit example_pulsar2a_ibert_gtx12_6gbps.bit r1 manage 11175.6 K 2014-05-07 - 23:04 HangYin  
Unknown file formatbit example_pulsar2a_ibert_gtx12_8gbps.bit r1 manage 11175.6 K 2014-04-25 - 00:48 HangYin ISE only! For Pulsar IIa FPGA programming, with the external clock frequency, GTX12 activated.
PNGpng fuses.PNG r1 manage 425.1 K 2016-04-19 - 20:14 ZijunXu  
PNGpng jumper_fmc.png r2 r1 manage 213.8 K 2014-04-18 - 19:09 ZijunXu  
PNGpng jumper_fmc2.png r1 manage 3.9 K 2014-04-24 - 17:12 ZijunXu  
PNGpng jumper_zone1.png r2 r1 manage 268.4 K 2014-04-18 - 19:09 ZijunXu  
PNGpng jumper_zone3.png r2 r1 manage 367.1 K 2014-04-18 - 19:09 ZijunXu  
Unknown file formatbit main.bit r2 r1 manage 2640.6 K 2014-04-26 - 18:03 ZijunXu  
Unknown file formatbit mezz.bit r2 r1 manage 630.7 K 2014-04-26 - 18:03 ZijunXu  
PNGpng polarized_Capacitors.PNG r1 manage 318.2 K 2014-04-18 - 17:31 ZijunXu  
PNGpng polarized_Capacitors2.PNG r1 manage 295.8 K 2014-04-18 - 17:31 ZijunXu  
Unknown file formatgz pulsar2b_initial_test.tar.gz r1 manage 85.2 K 2014-04-25 - 08:33 HangYin framework
PNGpng refclock_assignment.png r1 manage 414.4 K 2014-04-26 - 22:44 ZijunXu  
PNGpng resistor_distri.PNG r1 manage 305.2 K 2014-05-25 - 00:53 ZijunXu  
PNGpng rtm_connector.png r2 r1 manage 101.2 K 2014-04-26 - 01:08 ZijunXu  
PNGpng rtm_power.png r2 r1 manage 159.0 K 2014-07-09 - 00:47 ZijunXu  
PNGpng rtm_power2.png r1 manage 11.8 K 2014-04-26 - 00:58 ZijunXu  
PNGpng valtage_12_U16.PNG r2 r1 manage 121.0 K 2014-05-27 - 18:07 ZijunXu  
PNGpng valtage_12_U171821.PNG r3 r2 r1 manage 207.7 K 2014-07-09 - 00:43 ZijunXu  
PNGpng valtage_12_U23.PNG r2 r1 manage 137.6 K 2014-05-27 - 18:17 ZijunXu  
PNGpng valtage_1_U17.PNG r1 manage 256.5 K 2014-04-18 - 23:25 ZijunXu  
PNGpng valtage_1_U21.PNG r1 manage 255.3 K 2014-04-18 - 23:28 ZijunXu  
PNGpng valtage_1p0_fpga.PNG r1 manage 293.3 K 2014-04-19 - 00:48 ZijunXu  
PNGpng valtage_1p2_U23.PNG r1 manage 190.6 K 2014-04-18 - 23:31 ZijunXu  
PNGpng valtage_1p5_U22.PNG r1 manage 211.6 K 2014-04-19 - 00:29 ZijunXu  
PNGpng valtage_1p5_fpga.PNG r1 manage 285.6 K 2014-04-19 - 00:27 ZijunXu  
PNGpng valtage_1p8_U18.PNG r1 manage 371.6 K 2014-04-18 - 23:54 ZijunXu  
PNGpng valtage_1p8_U29.PNG r1 manage 235.1 K 2014-04-19 - 00:37 ZijunXu  
PNGpng valtage_1p8_fpga.PNG r1 manage 289.8 K 2014-04-19 - 00:44 ZijunXu  
PNGpng valtage_3p3_U16.PNG r1 manage 267.0 K 2014-04-18 - 23:18 ZijunXu  
PNGpng valtage_pim3p3.PNG r2 r1 manage 104.0 K 2014-05-27 - 18:04 ZijunXu  
Unknown file formattcl vivado_FMCLoop_scan.tcl r1 manage 2.9 K 2016-07-14 - 23:01 ZijunXu  
Unknown file formattcl vivado_FMCLoop_setup.tcl r1 manage 12.5 K 2016-07-14 - 23:01 ZijunXu  
Unknown file formattcl vivado_fabric_scan.tcl r1 manage 4.3 K 2016-04-21 - 02:27 ZijunXu  
Unknown file formattcl vivado_fabric_setup.tcl r2 r1 manage 7.6 K 2016-07-14 - 23:07 ZijunXu  
Unknown file formattcl vivado_rtms_scan.tcl r1 manage 9.2 K 2016-07-21 - 18:50 ZijunXu  
Unknown file formattcl vivado_rtms_setup.tcl r1 manage 14.6 K 2016-07-21 - 18:50 ZijunXu  
PNGpng voltage_summary.PNG r2 r1 manage 329.4 K 2014-04-24 - 18:01 ZijunXu  
JPEGjpg xilinx_FPGA.JPG r2 r1 manage 38.5 K 2016-07-14 - 21:31 ZijunXu from http://www.xilinx.com/support/documentation/errata/en206.pdf
Edit | Attach | Watch | Print version | History: r96 < r95 < r94 < r93 < r92 | Backlinks | Raw View | WYSIWYG | More topic actions
Topic revision: r96 - 2016-10-25 - ZijunXu
 
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