Open PlanAhead ISE 14.6

Create new project

Select "Imported Project" and import .ise file from tagged GLIB firmware directory (amc_glib_fw_3_2_0/fpga/prj/glib_v3_empty/)

  • make sure copy sources box is checked
  • click OK when "Unable to import ISE" message appears

Select "IP Sources" in Sources window in Project Manager ***Step not necessary if using trunk version***

  • right click on "dpbr_8_32", select "Source File Properties...", then select "Attributes" in Source File Properties window and uncheck "IS_LOCKED" option
  • right click on "dpbr_8_32", select "Upgrade IP", upgrade to highest version of Block Memory Generator available
  • right click on "dpbr8", select "Source File Properties...", then select "Attributes" in Source File Properties window and uncheck "IS_LOCKED" option
  • right click on "dpbr8", select "Upgrade IP", upgrade to highest version of Block Memory Generator available

Select "Add Sources..." in Sources window menu bar

  • select "Add or Create New Sources"
  • add "ttlk_mmcm.vhd" from amc_glib_fw_3_2_0/fpga/src/system/cdce/cdce_phase_mon_v2/pll/ directory
  • add "mmcm_no_ibufg.vhd" from amc_glib_fw_3_2_0/fpga/src/system/pll/ directory
  • Additional conditions for /trunk version:
    • import ipbus fw seperately from IPBus Firmware on CACTUS
    • import system_clk.ucf from tagged version ***must disable initial instance of system_clk.ucf ***
      • comment out all lines in file ---- does not pick up any clock signals during synthesis but will successfully go through all stages ]
      • from synthesis log file: Clock Information: ------------------ No clock signals found in this design

Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design

Timing Summary: --------------- Speed Grade: -1

Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found

=========================================================================*

    • import glib_top.vhd from tagged version ***must disable initial instance of glib_top.vhd***

Select "Synthesis Settings" from "Flow Navigator" panel

  • select "rebuilt" for "-netlist hierarchy*" option and apply changes

Select "Implementation Settings" from "Flow Navigator" panel

  • under Map (map) subheading, check "-u" option and apply changes [disables the removal of unnecessary/disabled logic]
    • If option is unchecked, will run into errors during mapping into LUTs stage: ERROR:MapLib:979 - LUT3 symbol "system/i2c/u0/u1/Mmux_rdbit11" (output signal=system/i2c/u0/u1/rdbit) has input signal "system/i2c/sda_to_core[1]" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven.

Select "Bitstream Settings" from "Flow Navigator" panel ***Step not necessary if using trunk version***

  • under Bit file generation (bitgen) subheading, check "-d" option and apply changes [disables a design rule check during bit file generation process]
    • If option is unchecked, will run into errors of following type: ERROR:PhysDesignRules:10 - The network <amc_port_tx_out(20)_OBUF> is completely unrouted.

To synthesize, select "Run Synthesis"

  • IP generation from listed IP sources will start
    • check marks will appear in the IP source boxes once generated

To implement, select "Run Implementation"

  • Critial warnings that appear
    • [Constraints 18-5] Cannot loc instance 'system/eth_B.phy_eth/sgmii/v6_emac_v1_5_inst/XST_GND' at site TEMAC_X0Y0, Unknown instance type 'GND' ["C:/Users/ksung/project_13/project_13.srcs/constrs_1/imports/src/system/setup/system_bench.ucf":34]
    • [Constraints 18-11] Could not find net 'cdce_sync_OBUF' ["C:/Users/ksung/project_13/project_13.srcs/constrs_1/imports/src/system/setup/system_bench.ucf":78]
    • [Constraints 18-10] Could not create constraint 'ROUTE' ["C:/Users/ksung/project_13/project_13.srcs/constrs_1/imports/src/system/setup/system_bench.ucf":78]

To make .bit file, select "Generate Bitstream"

Monitoring GLIB

  • connect Xilinx USB cable to JTAG connector (J12 for FPGA configuration and J13 for CPLD configuration)
  • select "Launch ChipScope Analyzer" from "Flow Navigator" panel
    • select JTAGChain and click on icon in upper left corner [Open Cable / Search JTAG Chain]
    • select "Window" from menu bar, then "New Unit Windows", and find "Device:0"
    • check "System Monitor Console" option and click OK

Flash firmware

  • select Launch iMPACT
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Topic revision: r3 - 2013-07-12 - StanislavaSevova
 
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