ALCT: Anode Local Charged Track Boards for the CSC Muon System

General Description:

In the CSC muon system, anode wires are hardwired together or `ganged' at the readout end in groups of 10-15 wires in order to reduce channel count. The anode wire group signals are fed into the AFEB boards, each of which contains a single 16-channel amplifier/constant-fraction discriminator chip. The output signals from the AFEB boards are sent into the ALCT boards, which handle triggering and readout of CSC anode information. Due to the various types of CSC chambers, there are 3 sizes of ALCT boards, handling 288, 384, and 672 anode wire group channels.

On the ALCT boards, the signals from each AFEB are first delayed by a programmable amount in order to perform an average time alignment of the anode signals across the chamber as well as chamber-to-chamber at a sub-bunch crossing level to about 2.2 ns precision. After the AFEB signals are received and time-aligned, they are then latched with the bunch crossing frequency and fed to a Xilinx Virtex FPGA mounted on a mezzanine card above the ALCT main board for pattern-finding and readout functions.

The algorithm used in the Virtex FPGA of the ALCT for determining muon segment position and bunch crossing in the anode view is illustrated below. Since the drift time can be longer than 50 ns, the hits are first stretched by 'one-shots' to 6 bunch crossings (150 ns) length. Then, a multi-layer coincidence technique in the anode LCT pattern circuitry is used to identify the bunch crossing. For each spatial pattern of anode hits, a low coincidence level, typically 2 or more layers, is used to establish timing, whereas a higher coincidence level, typically 4 layers, is used to establish the existence of a muon track. The general idea of a spatial pattern of CSC wire group hits is illustrated below:

Each pattern detector can detect a programmable "collision" pattern as well as a fixed "accelerator" pattern. The input data for the collision pattern detector are selected as shown below:

n-2.n-1.n.........Layer 1
....n-1 n.........Layer 2
........n.........Layer 3
........n n+1.....Layer 4
........n n+1 n+2.Layer 5
........n n+1 n+2.Layer 6

where n in this diagram is the key wire group number, which this particular pattern detector is searching the patterns for. The programming of the programmable collision pattern is implemented as a simple masking-out of the bits that we do not want to include in the pattern. The accelerator pattern is a vertical pattern of 6 layers all with strip n only.

Results from the muon pattern-finder logic are sent to the TMB (Trigger MotherBoard), which requires a coincidence between anode and cathode trigger information. In the case of a Level-1 Accept signal from the Global Trigger (distributed via the TTC system to the CCB in each peripheral crate), ALCT data are sequentially transmitted to the Trigger Mother Board and hence to the DAQ Motherboard. These data frames include a few words of ALCT trigger data and a much larger amount of ALCT raw hit data consisting of a time sequence of raw CSC anode wire-group hits that have been stored at the 40 MHz bunch crossing frequence by the ALCT2001. Typically 8 to 16 bunch crossings are read out for each wire group. FIFO data can also be read out much more slowly through VME access via the TMB board using a JTAG electrical interface to the ALCT, if necessary.

For self-monitoring and also for powering and controlling the AFEB cards, the ALCT contains a Slow Control section that supplies power to the AFEBs, controls AFEB thresholds, provides and controls the amplitude of test pulses to the AFEBs, and reads back power supply voltages and currents, as well as on-board temperature.

ALCT System Diagrams:

The detailed connections of the ALCT board to other parts of the CSC electronics are shown in the diagram below. See the ALCT specification document for a detailed description.

The internal workings of the ALCT board are shown in the following diagram (again, see the ALCT specification document for a detailed description):

Physical Implementation:

Mounted on each ALCT board is a mezzanine card containing the programmable gate array (FPGA) for the fast signals. There is a smaller gate array for the mezzanine card mounted on the 288 and 384 channel ALCT boards (Xilinx XCV600), and a larger one (XCV1000) for the 672 channel board.

Pictures of the three types of boards with their aluminum stiffener plates attached (click on each for a really detailed view):

ALCT288:

ALCT384:

ALCT672:

Picture of the XCV1000 mezzanine board (mounted face down on the ALCT boards):

Main Links:

• The ALCT specification document is the place to go for detailed information (last update 16-JUL-2014).
• The Main FPGA firmware files directly from Alex Madorsky

ALCT testing:

• The updated UCLA testing and UCLA DB page for both (ALCT and TMB) board testing and database page, updated at least after November 2013 (the old one, circa 2007, may be found here).
• Peripheral crate testing procedures from the ISR and B904 (covers both ALCT, TMB, etc.)
• Other files from production ALCT board testing:
  • The latest test board schematics.
  • Full, updated set of (zipped) ALCT Test Board design and layout files.
  • Probably non-updated version of ALCT Test Board design and layout files from Gennady Zhmakin.

Other Links:

• A detailed description from 2001 that is in the Trigger TDR Chapter 11.
• ALCT2001-384 layout files by Valerie Iatsioura
• The ALCT2001 Mezzanine card schematics and layout, ALCT-672 layout, and ALCT-288 layout files by Misha Kan
• A general description of the ALCT board-level calibration procedure
• Software for testing the ALCT.
• Testing procedure for the ALCT.
• Prototype testing: see various powerpoint presentations from July 2001 to January 2002.
• Older prototypes and design files, mostly obsolete:
  • Older Vlad Sedov layout files: zipped eps files (from Mar, 2001)
  • ALCT2000-384 (384-channel version):
  • A detailed ALCT2000 design manual, simplified Users' guide, initial description
  • ALCT2000-384 prototype board design schematics, bill of materials, OrCad design files: zipped files
  • ALCT2000-384 FPGA design: Altera files
  • ALCT2000 radiation test results web page and technical note
  • Even earlier prototypes: ALCT99 (and CLCT99), which were 9U VME cards, and LCT48 (and CLCT48, from 1998)