SR1 Setup Status

Here informations on the current SR1 status.

lpGBT configuration (with VLDB+)

Fibers cassette setup:

fibers cassette SR1.png
caption text

At DAQ workstation, configure the lpGBT on VLDB+ over PiGBT (Rasberry Pi):

  1. if needed, reboot PiGBT by pressing RESET button, it will also trigger restart on VLDB+
  2. open PiGBT web page, it will ask to initialize - do so, select "Real lpGBT", I2C address 127 now, PiGBT must find this address and show it in the drop-down list
  3. go to Registers tab and load the recent register config file
  4. some Core parameters might still not be set - check them: the MODE must be Tranciever, and others (Clocks, High speed parameters) according to Nico's instructions in "lpGBT Configuration" below.
  5. at the end the PiGBT web page must show green check mark at the top right, and in clocks (not sure now?) and on the felix server flx-info GBT must have 1 channel aligned.

PiGBT Setup - Core:

core SR1.png
caption text

PiGBT Setup - Clocks: (EPCLKs OFF)

clocks SR1.png
caption text

PiGBT Setup - High-speed:

high-speed SR1.png
caption text

FELIX Setup:

Firmware can be found on:


To load the firmware, one can use

fflashprog -f 3 firmware_path.mcs prog
sudo reboot

After loading fw:


set felix lpgbt to 10G mode:

cd /home/itkfelixstrips/lpgbt_debugging_tools/set_flx_datarate

check that link is aligned:

flx-info GBT
(should return 1 aligned and 3 channels not aligned, sometimes it shows 2 aligned channels for a short time period)

Then, Check that AMAC polarity is inverted:

flx-config -d 0 getraw -b 2 -r 0xD000 
; value of register should be 0x00000008. If not, run
flx-config -d 0 setraw -b 2 -r 0xD000 -o 0 -w 64 -v 0x008


elink SR1.png
caption text


Screenshot from 2021-07-29 16-10-30.png
Elinkconfig for SR1 module with AMAC and Star chips used with VLDB+ and FLX71 23-3-2021 at 15h02 firmware

If elinks are not configured, use the same script source scripts/ FLX712 as for GBT test vehicle?

Example of FELIX.json file:

caption text

Example of star setup json file:

starsetup SR1.png
caption text

Initialize GBT links (with GBTx Test board)

From Felix Server:

Configuration of FELIX in SR1:

  1. check that GBT link 0 is aligned:
     flx-info GBT 
  2. if not, run:
    (should return 1 aligned and 3 channels not aligned)
  3. run
    Read Cfg, should look like in picture:
    Elink configuration when initializing GBT links to perform scan.
  4. if not, run the script:
     source scripts/ FLX712 
    (if it doenít work kill felixcore)
  5. Check that AMAC polarity is inverted:
    flx-config -d 0 getraw -b 2 -r 0xD000 
    ; value of register should be 0x00000008.
  6. If not, run
    flx-config -d 0 setraw -b 2 -r 0xD000 -o 0 -w 64 -v 0x008
  7. Start felixcore: ( it might crash after a while, remember to check that itís still active) with:
    /home/itkstrips/FELIXSw/x86_64-centos7-gcc8-opt/felixcore/felixcore-d 0 -t 1 --data-interface enp96s0f0 --monitoring-interface enp96s0f0 --trace -p 12350 -r 12340 

(NOTE: the script takes care of steps 3-7 Ė> remember to kill felixcore if running)

Initialize AMAC, power up the module, and run a scan from DAQ server (when elinks are already set up)

scan SR1.png
Example of scan output

From DAQ server:

Configure AMAC: must be configured to interact with Star chip:

  1. cd ./softwareFELIX/YARR/build/
  2. ./bin/write_amac_new
    (you shall see the current changing on the power supply, from 0.05 to 0.10-0.11) write_amac_new sends setid to the amac, using idpads (=2 on our amac) and sets the amac id to 21; then it runs the module power up sequence.
Run scan:
  1. cd ./softwareFELIX/YARR/build/
  2. bin/scanConsole -c ../configs/connectivity/example_star_setup.json -r ../configs/controller/felix.json -p -s ../configs/scans/star/std_analogscan.json
    # or
    bin/scanConsole -c ../configs/connectivity/example_star_setup.json -r ../configs/controller/felix.json -p -s ../configs/scans/star/diff_noisescan.json
    (I get an empty scan at the moment, so I might need to update this instruction)

Elink configuration to interact with the chip

Test using the VLDB+ board and the adapter with the Strips firmware.

  1. Get phase1 firmware here: Phase I firmware
  2. Use these scripts:
    (lpGBT only works with FLX712)
  3. For FromHost elinks do either: * enable 4-bit elinks 000, 004, 008, 00c in 8b10b mode. This tells the firmware that those are R3L1 links that only work in bypass mode and have no trickle configuration memory * enable 4-bit elinks 000, 004, 008, 00c in direct mode, and the bypass elinks 018, 01a 01c and 01e, correspondingly
  4. For ToHost elinks, enable all 8b10b links first, capturing some data with fdaq, and then running fcheck to see which links the data comes from
  5. For AMAC links, they are on EC links of each GBT link when
    script is used.

Electric parameters

Expected power consumption in SR1:

Component Voltage (V) Current (A) [base - configured] Note
ITSDAQ GBTx Test Vehicle 1V5a 1.5V DC 0.33 - 0.50  
ITSDAQ GBTx Test Vehicle 1V5b 1.5V DC 0.07 - 0.24  
ITSDAQ GBTx Test Vehicle 3V3 3.3V DC 0.14 - 0.17  
Module 11.01V DC 0.052 - 0.107 Dual cable for surge stability
VLDB+ with Mezzanine 10V DC 0.579  

ToDo List

  • [13/04/21] Interference with power lines: 50Hz noise observed on hybrid module pins. Change in power supply ground could fix this.
  • [13/04/21] Get new scope probes


Common issues and fixes

  1. When configuring lpGBT, RX links lock but TX don't

This is due to flx-init. After calling flx-init, on the felix server, run:

python2 lpgbt_debugging_tools/set_flx_datarate/

Useful Links

YARR Strips repository

lpGBT manual - it is quite full, from hardware to programming, includes configuration and slow control frame format. You need to register on their mailing list for access, it takes a couple days to get aproved.

VLDB+ manual

TDAQ documentation page see Felix User Manual. FELIX info from Nikhef.

BNL 711-712 manual - how to connect FLX712 etc.

TDAQ documentation sources

Strip System Architecture - a schema of the full system by Craig Sawyer (RAL).

Petal Star Hybrids - schematics of the hybrid module.

Detector components:

Module, EoS, Hybrid; HCC & ABC; power board, DCDC converter & AMAC.

Overall system:

ITk Strips TDR

ITk DAQ requirements

DCS requirements for HL-LHC - as a starting point see "Figure 2.3: On-detector front-end interface schema showing the two paths for controls data and associatedpowering" with the full DCS system, communicating over FELIX and EMP.


atlas-itk-strips-sr1 (ITk Strips at CERN)
Topic attachments
I Attachment History Action Size Date Who Comment
PNGpng FELIXjson.png r1 manage 245.6 K 2021-04-13 - 11:21 GabrieleDAmen  
PNGpng Screenshot_from_2021-07-29_16-10-30.png r1 manage 227.8 K 2021-07-29 - 16:11 OlivierArnaez ElinkConfig for VLDB+ with AMACandStars in SR1 (July21)
PNGpng clocks_SR1.png r1 manage 24.3 K 2021-04-13 - 11:21 GabrieleDAmen  
PNGpng core_SR1.png r1 manage 96.6 K 2021-04-13 - 11:21 GabrieleDAmen  
PNGpng elink_SR1.png r1 manage 490.5 K 2021-04-13 - 11:21 GabrieleDAmen  
PNGpng felix.png r1 manage 286.8 K 2021-04-01 - 16:09 GabrieleDAmen  
PNGpng fibers_cassette_SR1.png r1 manage 892.9 K 2021-04-13 - 11:21 GabrieleDAmen  
PNGpng high-speed_SR1.png r1 manage 36.0 K 2021-04-13 - 11:21 GabrieleDAmen  
PNGpng scan_SR1.png r1 manage 34.9 K 2021-04-13 - 11:21 GabrieleDAmen  
PNGpng starsetup_SR1.png r1 manage 139.9 K 2021-04-13 - 11:21 GabrieleDAmen  
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Topic revision: r15 - 2021-08-04 - OlivierArnaez
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