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FEROL (FrontEnd ReadOut Link) - User manuel ver 1.00

1 Introduction

The FRL (FED Read-out Link) is the first element of the Data Acquisition for CMS. It has two functions:

  • It moves data out of FEDs and push them to the first stage of the FED builder through the FEROL card.
  • It manages up to 2 events fragments coming from two FEDs (see figure 1), each of them will be sent to the DAQ system independently. This feature has the advantage to increase the using of the bandwidth.
CMS Data Acquisition System Figure: CMS Data Acquisition System

The total number of this board is 512. They will collect events fragments coming from more or less 650 FED’s.

2 Description

The FRL is descripted in another manual. Here we will focus only on the FEROL card which is new. This card is based on PCIx bus (64-bit @ 100MHz) to be compliant with the existing FRL card.

The FEROL will receive data from the FRL (via PCIx bus 64bit@100Mhz) or from one or two optical link input(s) (on FEROL card). Data coming from FED are sent using the SLINK64 format (64-bit + Uctrl). The 'Uctrl' bit specifies if the 64-bit is a data word or a control word (Header or Trailer which encapsulate the fragment). Unfortunatly this bit will disappear in the 10 Gb/s stream. The function of the FEROL header is to replace the function of this 'Uctrl' bit.

Data coming from FED will be divided in block(s) of 4Kbytes max (FEROL header included). Only one Fragment per block (but can be multiple blocks per fragment). The two first 64-bit words are the FEROL header which specifies what is inside the block (beginning of the fragment, end of the fragment, number of word inside the block, the block number if a fragment is divided in multiple blocks, and some reserved bits).

  • first 64-bit word
    • b[63..48] : 0x575A
    • b[42..32] : block number (starting with 0; increment for each block of 4kB of the current fragment)
    • b[31] : '1' if it is the first block of the current fragment
    • b[30] : '1' if it is the last block of the current fragment
    • b[9..0] : number of data in the block (count in 64-bit words)
  • second 64-bit word
    • b[43..32] : FED number corresponding to the stream
    • b[23..0] : trigger of the current fragment
  • All bits not specified are reserved and should be '0'.
The FEROL Header

Figure: The FEROL Header consists of two 64 bit words.

These blocks will be sent to the 10Gb/s ethernet link using the TCP/IP (simplified version). The header of the block will help the receiver to reformat each fragment.

2.1 FEROL PCIx

The FEROL is a PCI card based on the PCIx protocol able to communicate with the FRL card. The PCIx bus is used to control and monitor the card and to receive 64-bit data coming from FRL SLINK connectors. This PCI-X bus runs at 100 MHz. The FEROL is a pure PCI-slave card.

The FEROL is configured with 2 base addresses. The one to control and monitor the card is used in single data access mode. The second is used to receive the data from the FRL in burst mode.

The FRL main FPGA firmware will memorize the second baseaddress of the FEROL during the PCI configuration (at PC boot-time). This avoids the need for software to configure this address. The FRL will use the memorized baseaddress to send the data received from the SLINK connectors.

2.2 FEROL Input Optical Link

The FEROL is able to receive data FED from one or two optical 5 Gbps links. If data is received from both links, the have to be operated at the same speed.

Data received via the optical links must have the same format as data received via the FRL SLINK connectors. Data can’t be received from via the SLINK - PCIx chain and the optical link simultaneously. (The throughput would be too high to share the same QDR memory and would hence lead to excessive backpressure.)

The protocol used to receive data over the optical link is described in the Appendix A.

This protocol uses 8/10 bit encoding. Therefore the effective data throughput is 4Gb/s (500 Mbytes/s). This is 20% more compared to the SLINK64 protocol.

2.3 FEROL internal event generator

The FEROL firmware includes a internal event generator (which can sustain the 10 Gb/s throughput). This event generator is more simple that the one implemented inside the FRL. It allows you to generate fragments (with fixed size) or to use a FIFO (which has 1000 inputs) to record up to 1000 different descriptors.

The trigger:

  • you can send a trigger for each fragment. First write 0x18 to the function GEN_TRIGGER_CONTROL_FED0; and for each trigger write 0x19 at the same offset. With this trigger mode the fragment length will be specify by the function GEN_EVENT_LENGTH_FED0 (if it doesn't change the fragment length will be the same for each trigger)
  • you can generate trigger in loop, one after the other:
    • if the word count is fixed, the next event is sent as soon as the current event is finished (fragment length will be the same all the time, specified by the function GEN_EVENT_LENGTH_FED0); (To do this write 0x1A to function GEN_TRIGGER_CONTROL_FED0 and 0x14 to stop it)
    • if the FIFO (descriptors) is used, as soon as a event is finished the time specified in the descriptor will has to elapse before the next event is sent; (To do this write 0x10 to offset function GEN_TRIGGER_CONTROL_FED0 and 0x0 to stop it)
You should use the appropriatted offset for the Event Generator FED1.

2.4 FEROL Output ethernet 10 Gb

The FEROL use a 10Gb/s Ethernet connection to send the data FED to the DAQ system. The interface is not controlled and managed by a processor. The TCP/IP protocol used is manage by a state machine inside the FPGA firmware and simplified (see annexe B).

There will be to TCP state machine one for each SLINK connector. We don’t merge data coming from the both SLINK connection as it was in the previous version used up to 2013.

3 Functionality

Here, we will describe how data move from FED to the DAQ FED builder system. Two options will be explain, the one where data come from SLINK connector and the other where they are coming from optical link.

4 FEROL Designs

4.1 FRL Design 0

  • Vendor ID: ECD6; Device ID: FF10
  • R/W: bit can be read and write
  • R: bit is read only.
  • W: bit can write ‘1’ or ‘0’, read is ‘0’
The design 0 is used in normal operation. Data is input by the front connector. The data of the both connectors can be merged or used independently (input 1 or input 2).

Before using the FRL to receive data fragment from FEDs, it should be initialized. In the next paragraphs, the details of each setup will be explained. They will be followed by a description of each functions and a summary table.

4.1.1 SETUP SLINK

  • In COMMAND mode, setup of the board
  • In DAQ mode setup to receive data.

4.1.2 PCIx Configuration


Offset: 0x0000  mask: 0xFFFFFFFF  CONFIG   name: ConfigStart                           mode: R/W
   This is the beginning of the configuration space. It is put here in the table as r/w item so that it 
   can be read out and written back after a change of the firmware loaded from the eprom into the
   FRL fpga

Offset: 0x0000  mask: 0x0000FFFF  CONFIG   name: Vendor_Id                             mode: R
   This register corresponds to the Vendor ID of the board (function 2 of the card).
   Value: ECD6

Offset: 0x0000  mask: 0xFFFF0000  CONFIG   name: Device_Id                             mode: R
   This register correspond to the Device ID of the FRL logic element (function 2 of the card)
   Value: FF10

Offset: 0x0004  mask: 0x00000002  CONFIG   name: Memory_Space                          mode: R/W
   This bit when set by the BIOS able card to be accessed in memory space.

Offset: 0x0004  mask: 0x00000004  CONFIG   name: Bus_Master                            mode: R/W
   This bit when set by the BIOS able the card to do master access on PCI bus

Offset: 0x0010  mask: 0xFFFFFFF8  CONFIG   name: BAR0                                  mode: R/W
   This register is write by the BIOS to indicate at which address the card responds to a PCI access
   
Offset: 0x0048  mask: 0xFFFFFFFF  CONFIG   name: CompileVersion                        mode: R
   This register will be increment to the 16 lower bits at each design compilation. The upper 16-bit corresponds to the design number which is 0xF020.

Offset: 0x0048  mask: 0xfff00000  CONFIG   name: FirmwareType                          mode: R
   The firmware type. 

Offset: 0x0048  mask: 0x000f0000  CONFIG   name: HardwareRevision                      mode: R
   The hardware revision.

Offset: 0x0048  mask: 0x0000ffff  CONFIG   name: FirmwareVersion                       mode: R
   The firmware version.

Offset: 0x0050 mask: 0x000000FF  CONFIG    name: Geographic_Address                     mode: R
  This number indicates the greographical position in the CompactPCI crate. Starting from rigth side, position 0 is the controller.
  
Offset: 0x005C  mask: 0xFFFFFFFF  CONFIG   name: SNa                                   mode: R
      This register returns the lower 32-bit of the board serial number.

Offset: 0x0060  mask: 0xFFFFFFFF  CONFIG   name: SNb                                   mode: R
      This register returns the bit 63 to 32 of the board serial number.

Offset: 0x0064  mask: 0x00000FFF  CONFIG   name: SNc                                   mode: R
      This register returns the upper 12-bit of the board serial number.  
     

4.1.3 Functions

Offset: 0x0000  mask: 0xFFFFFFFF           name: CONTROL                               mode: R/W
   This function is used to generate global reset and global settings 
   Bit(14):  select the data source  bit(15..14) =  00  PCIx (via the SLINK copper) --- 01 internal generator --- 10 SLINK5Gb --- 11 SLINK 10Gb
   Bit(15):  select the data source 
   Bit(17) : write a ‘1’ will reset all the board. You do not need to write a ‘0’.
   Bit(19): writing '1' will trigger the reading of the serial number and the MAC from the PROM to the internal registers. 
             This is automatically triggered at power up and usually does not need to be repeated.
   Bit(20): write a '1' start the BIST of DDR2 memory (done automatically at the FPGA boot time)
   Bit(21): read a '1' the BIST (DDR2) is succefull ; read a '0' BIST out with error.
   Bit(22): read a '1'  BIST (DDR2) was done , read a '0' BIST is currently in execution.
   Bit(23): set to '1' to init faster the DDR2 memory interface (should be used for simulation only).
   Bit(24): write a '1' start the BIST of QDRII memory (done automatically at the FPGA boot time)
   Bit(25): read a '1' the BIST (QDRII) is succefull ; read a '0' BIST out with error.
   Bit(26): read a '1'  BIST (QDRII) was done , read a '0' BIST is currently in execution.
   Bit(27): '0' after reset. Set to '0' the QDR is used as socket buffer. Set to '1', DDR2 is used as socket buffer.
   Bit(28) : write a '1', Disable the memory BIST on LED front panel  '0' (by default) BIST result is displayed on LED front panel.
   Bit(29):  write a '1' will reset the TCP dump pointers.
   Bit(30) : write a '1' will blink the leds to indicate that the SFP+ has to be exchanged.
   Bit(31) : write a ‘1’ will latch the Registers value read by functions 0x43A0 to 0x43C4 ??????????

Offset: 0x0000  mask: 0x0000C000           name: FRAGMENT_DATA_SOURCE                  mode: R/W
Offset: 0x0000  mask: 0x00020000           name: SOFTWARE_RESET                        mode: R/W
Offset: 0x0000  mask: 0x00080000           name: read_SN_MAC                           mode: R/W
  The Serial & MAC address is also read automatically after a reset (hard and soft)
Offset: 0x0000  mask: 0x08000000           name: TCP_SOCKET_BUFFER_DDR                 mode: R/W
Offset: 0x0000  mask: 0x20000000           name: FEROL_EMULATOR_MODE                   mode: R/W
Offset: 0x0000  mask: 0x40000000           name: BLINK_LEDS                            mode: R/W
Offset: 0x0000  mask: 0x80000000           name: LATCH_REGISTERS                       mode: R/W

Offset: 0x0008  mask: 0xFFFFFFFF           name: Mol_Clock_Setup                       mode: R/W
  Write the value 0xCC004003 to setup the internal clock of the Mol to use the SLINKexpress. Only available in th MOL!

Offset: 0x0008  mask: 0xFFFFFFFF           name: HRD_MAC_L                             mode: R
   Return the lower part of the MAC address of the board (programmed in a eeprom memory on board)
   Only available on FEROL card -- MAC[31..0]
Offset: 0x000C  mask: 0x0000FFFF          name: HRD_MAC_H                              mode: R
   Return the higher part of the MAC address of the board (programmed in a eeprom memory on board)
   Only available on FEROL card -- MAC[47..32]
   
Offset: 0x0010  mask: 0xFFFF0000           name: QDR_High_address                      mode: R/W
   Specify the Higer part of the address (...16) to access the QDR memory, the lower part (15..0) is specify by the offset of the access BarAddress(1)   

Offset: 0x0014  mask: 0xFFFF0000           name: DDR_High_address                      mode: R/W
   Specify the Higher part of the address (...16) to access the DDR memory, the lower part (15..0) is specify by the offset of the access BarAddress(1)   

Offset: 0x0020  mask: 0xFFFFFFFF           name: pointer_debug_S_TCP                   mode: R
   Pointer of the last data written in the memory where the dump of TCP header packets are recorded.
   For SENDER part. DDR or QDR (depending of the memory used for buffer TCP STREAMs).
   This pointer is reset by softreset.

Offset: 0x0024  mask: 0xFFFFFFFF           name: pointer_debug_R_TCP                   mode: R
   Pointer of the last data written in the memory where the dump of TCP header packets are recorded.
   For RECEIVER ACK part. DDR or QDR (depending of the memory used for buffer TCP STREAMs)
   This pointer is reset by softreset.   

4.1.4 General Functions 5Gb LINK

Offset: 0x2000  mask: 0xFFFFFFFF           name: Link5gb_setup                         mode: R/W
   This function is used to setup the 5Gb LINK
Offset: 0x2000  mask: 0x00C00000  name: Link5gb_serdes_up                              mode: R
   '3' indicates that the both 5gb SERDES went successfully through the reset procedure and the PLL is now locked. The links can be used now (this item is convenient for the software)

   Bit(29) : indicates that the SERDESes of both links are powered off. (There is only a common power switch for boht SERDESes
   Bit(31) : indicates that the PLLs of both SERDESes are powered off.

Offset: 0x2004  mask: 0xFFFFFFFF           name: L5gb_serdes_reconf                    mode: R/W 
   Bit(31..0) : used by expert to reconfigure the SERDES parameters.
   
Offset: 0x2008  mask: 0xFFFFFFFF           name: L5gb_status_serdes                    mode: R 
   Bit(2)  : a '1' indicates the RX PLL of link 0 is locked
   Bit(3)  : a '1' indicates the RX PLL of link 1 is locked
   Bit(4)  : a '1' indicates the RX frequency for link 0 is locked
   Bit(5)  : a '1' indicates the RX frequency for link 1 is locked
   Bit(6)  : a '1' indicates the locking of the PLL clock in PLL.
   Bit(7)  : a '1' indicates that the SERDES block in the FPGA successfully loaded its configuration parameters from the configuration block in the FPGA.
   Bit(15..8) : these bits indicate the successful recognition of patterns and a successful synchronization of byte streams in the link. It seems the every link has to independent byte streams for which one bit indicates the pattern recognition and on the successful stream synchronization.
   Bit(31..16) : reserved

Offset: 0x2040  mask: 0xFFFFFFFF           name: gen_error_stimuli_debg                mode: W
   This control word exists only in the firmware which is used for debugging to GENERATE a AMC13 like data stream. It is not in the firmware of the production system.
   Writing a '1' to the following bits triggers the generation of an error for test purposes. Bits 0 and 1 act on the receiving side of the link and will stay in the final design. The other
bits act on the event generator which will not be contained in the final design. 
   Bit(0) : Generate a CRC error on ACK receiver
   Bit(1) : Generate an error on Receiver Frame
   Bit(17..2) : set a backpressure on receiver part
   Bit(24) : Generate an error on Ack receiver (FED side)
   Bit(25) : Generate an error on Frame FED side
   Bit(26) : Generate an error on Seq number FED side
   Bit(27) : Generate a CRC error on sender FED side
   Bit(28) : generate an error on WC sender FED side
   Bit(29) : Request a sync (reset the sequence number
   Bit(30) : Generate a CRC error on Event fragment
   Bit(31) : Generate an error on 1 bit inside the event

          
Offset: 0x2048  mask: 0xFFFFFFFF           name: L5gb_send_packet_fed_debg             mode: R
   Only available in the debug firmware to emulate the AMC13 (not in production version firmware)
   Bit(31..0) : counts the total number of packets (data or command) sent (from FED side)

Offset: 0x204C  mask: 0xFFFFFFFF           name: L5gb_received_ack_fed_debg            mode: R
   Only available in the debug firmware to emulate the AMC13 (not in production version firmware)
   Bit(31..0) : counts the number of acknoledges received (from FED side)  
    
Offset: 0x2058  mask: 0xFFFFFFFF           name: L5gb_rexm_packt_debg                  mode: R
   Only implemented in the sender firmware used for debugging (amc13 emulator)
   Bit(31..0) : counts the number of packets retransmitted (from FED side)
       
Offset: 0x2060  mask: 0xFFFFFFFF           name: L5gb_event_sent_debg                  mode: R
   Only implemented in the sender firmware used for debugging (amc13 emulator)
   Bit(31..0) : counts the number of event fragments sent (from FED side)
   
Offset: 0x2190  mask: 0xFFFFFFFF           name: L5gb_trigger_debg                     mode: R/W
   Bit(0) : a '1' will execute one PCI trigger (read all the time '0')
   Bit(1) : a '1' will cause events to be generated in loop mode
   Bit(2) : a '1' will stop the loop mode (was '0' in orginal documentation... check with dominique !!???)
   Bit(3) : a '1' will load the word count of register  L5gb_event_para2_debg.
   Bit(4): write a one will start the functionality of the event generator, this be should be set the last, when all other bits are set.
   Bit(5): write a ‘1’ will reset the RND memory.

Offset: 0x2194  mask: 0xFFFFFFFF           name: L5gb_event_num_debg                   mode: R/W
   Bit(23..0) : sets the initial event number used in the generator. This value will be increased by '1'
   for each trigger. Reading this register will return the actual trigger number. 
         
     
Offset: 0x219C  mask: 0xFFFFFFFF           name: L5gb_event_para1_debg                 mode: R/W
   Bit(11..0) : specifies the source ID used in Event generator    
   Bit(27..16) : specifies the Bunch Crossing number used in the event generator

Offset: 0x21A0  mask: 0xFFFFFFFF           name: L5gb_event_para2_debg                 mode: R/W
   Bit(23..0) : specifies the word count used in Event generator (PCI trigger enable)
      This value specifies the number of 64bit words!

Offset: 0x21A4   mask: 0xFFFFFFFF          name: L5gb_EventDesc_fifo                   mode: R/W
   Bit s15...0 : wordcount in 64 bit words, Bits 31...16: delay in ??? ns steps

4.1.4.1 SLINKXpress LINK 0

Offset: 0x3000  mask: 0xFFFFFFFF           name: Link5gb_setup_SlX0                    mode: R/W
   This function is used to setup the 5Gb LINK0
Offset: 0x3000 mask: 0x0000000f            name: Link5gb_SFP_status_SlX0               mode: R
  Bitfield summarizing the status of the SFP of link 0
Offset: 0x3000 mask: 0x00000001            name: Link5gb_SFP_txfault_SlX0              mode: R
   Bit(0)  : Indicates a TX_fault (SFP output) for LINK 0. For example this could indicate a laser problem.
Offset: 0x3000  mask: 0x00000002           name: Link5gb_ena_SFP_L0                    mode: R
   Bit(1)  : a '1'  indicates that the SFP is enabled.
Offset: 0x3000 mask: 0x00000004            name: Link5gb_SFP_detected_SlX0             mode: R
   Bit(2)  : a '1' indicates that an SFP is present in the cage of LINK 0; a '0' indicates that no SFP is present or that it is badly inserted.
Offset: 0x3000 mask: 0x00000008            name: Link5gb_SFP_rxloss_L0                 mode: R
   Bit(3)  : a '1' indicates an RX signal loss in the SFP of LINK 0. Internally the SFP has thresholds. If the signal strength drops below this threshold this bit is activated.
 Offset: 0x3000  mask: 0x00400000  name: Link5gb_serdes_up_L0                          mode: R
   Bit(22) : indicates that the SERDES of LINK 0 went successfully through the reset procedure and the PLL is now locked. The link can be used now.
 
Offset: 0x3010  mask: 0xFFFFFFFF           name: L5gb_i2c_sfp_SlX0                     mode: R/W
   Bit(7..0) : data to write or data returned from a read access
   Bit(15..8) : address of the register to access
   Bit(16) : returns a '1' when the access is completed. (has to be polled to determine the validity of the data during a 'read' access)
   Bit(24) : a '1' indicates a read access; a '0' indicates a write access '0'
   Bit(31..25,24) : specifies the I2C chip address. See data sheet for details. The address A0 contains hardcoded information about the SFP whereas the address A2 contains parameters which can be changed from their default values (e.g. thresholds for alarms). Beware that bit 24 needs to be set to '1' to perform a read access (i.e. in this case the addresses are changed to A1 and A3 resp). 

Offset: 0x3014  mask: 0xFFFFFFFF           name: L5gb_OLstatus_SlX0                    mode: R    
   Bit(31..0) : additional status to debug the Optical Link SLINKXpress0

Offset: 0x3018  mask: 0xFFFFFFFF           name: L5gb_slink_status_reset_SlX0          mode: R/W 
   Bit(0) : '1' indicates the reception of a fragment with a trigger number out of order ( 'syn-lost-draining' )
   Bit(31) : write a '1' to reset the status registers and counters
   
Offset: 0x3020  mask: 0xFFFFFFFF           name: L5gb_Seq_n_data_SlX0                  mode: R W   
   Bit(31..0) : contains the current packet sequence number for the incoming data packets. Beware that the sequence numbers for data-packets and those for command-packets are independent. 
   
Offset: 0x3024  mask: 0xFFFFFFFF           name: L5gb_Seq_n_Cmd_SlX0                   mode: R    
   Bit(31..0) : contains the current packet sequence number for command packets (send from FEROL side).

Offset: 0x3028  mask: 0xFFFFFFFF           name: L5gb_good_event_SlX0                  mode: R    
   Bit(31..0) : counts the number of correctly received event fragments. This is the number of fragments without SLINK-CRC error.
   
Offset: 0x302C  mask: 0xFFFFFFFF           name: L5gb_bad_event_SlX0                   mode: R    
   Bit(31..0) : count the number of bad events received, i.e. events with a SLINK-CRC error. 

Offset: 0x3030  mask: 0xFFFFFFFF           name: L5gb_bad_pack_received_SlX0           mode: R    
   Bit(31..0) : count the number of bad packets received. Bad packets are packets where an internal CRC error is detected (a CRC which is generated for the transfer of the packet over the optical link. This is different from the SLINK crc.)

Offset: 0x3034  mask: 0xFFFFFFFF           name: L5gb_Backpressure_SlX0                mode: R  
   Bit(31..0) : Counts how often a packet could not have been acknowledged since there was no free buffer available.
   
Offset: 0x3038  mask: 0xFFFFFFFF           name: L5gb_tot_pckt_rcv_SlX0                mode: R
   Bit(31..0) : counts the total number of packets (data or command) received (bad and good) 
   
Offset: 0x303C  mask: 0xFFFFFFFF           name: L5gb_received_packt_SlX0              mode: R
   Bit(31..0) : counts the number of good data packets received
   
Offset: 0x3040  mask: 0xFFFFFFFF           name: L5gb_trg_received_SlX0                mode: R
   Bit(31..0) : current trigger number received in the last packet
   
Offset: 0x3054  mask: 0xFFFFFFFF           name: L5gb_send_ack_cmd_SlX0                mode: R
   Only implemented in the sender firmware used for debugging (amc13 emulator)
   Bit(31..0) : counts the number of acknowledge-packets plus command packets sent (i.e. the number of packets in the direction from the FEROL to the Sender) 
 

4.1.4.2 SLINKXpress LINK 1

Offset: 0x4000  mask: 0xFFFFFFFF           name: Link5gb_setup_SlX1                    mode: R/W
   This function is used to setup the 5Gb LINK1
Offset: 0x4000 mask: 0x0000000f                  name: Link5gb_SFP_status_SlX1         mode: R
  Bitfield summarizing the status of the SFP of link 0
Offset: 0x4000 mask: 0x00000001            name: Link5gb_SFP_txfault_SlX1              mode: R
   Bit(0)  : Indicates a TX_fault (SFP output) for LINK 0. For example this could indicate a laser problem.
Offset: 0x4000  mask: 0x00000002           name: Link5gb_ena_SFP_L1                    mode: R
   Bit(1)  : a '1'  indicates that the SFP is enabled.
Offset: 0x4000 mask: 0x00000004            name: Link5gb_SFP_detected_SlX1             mode: R
   Bit(2)  : a '1' indicates that an SFP is present in the cage of LINK 1; a '0' indicates that no SFP is present or that it is badly inserted.
Offset: 0x4000 mask: 0x00000008                  name: Link5gb_SFP_rxloss_SlX1         mode: R
   Bit(3)  : a '1' indicates an RX signal loss in the SFP of LINK 1. Internally the SFP has thresholds. If the signal strength drops below this threshold this bit is activated.
Offset: 0x4000  mask: 0x00400000                 name: Link5gb_serdes_up_SlX1          mode: R
   Bit(22) : indicates that the SERDES of LINK 0 went successfully through the reset procedure and the PLL is now locked. The link can be used now.
  
Offset: 0x4010  mask: 0xFFFFFFFF           name: L5gb_i2c_sfp_SlX1                     mode: R/W
   Bit(7..0) : data to write or data returned from a read access
   Bit(15..8) : address of the register to access
   Bit(16) : returns a '1' when the access is completed. (has to be polled to determine the validity of the data during a 'read' access)
   Bit(24) : a '1' indicates a read access; a '0' indicates a write access '0'
   Bit(31..25,24) : specifies the I2C chip address. See data sheet for details. The address A0 contains hardcoded information about the SFP whereas the address A2 contains parameters which can be changed from their default values (e.g. thresholds for alarms). Beware that bit 24 needs to be set to '1' to perform a read access (i.e. in this case the addresses are changed to A1 and A3 resp). 
  
Offset: 0x4014  mask: 0xFFFFFFFF           name: L5gb_OLstatus_SlX1                    mode: R    
   Bit(31..0) : additional status to debug the Optical Link SLINKXpress1
  
Offset: 0x4018  mask: 0xFFFFFFFF           name: L5gb_slink_status_reset_SlX1          mode: R/W 
   Bit(0) : '1' indicates the reception of a fragment with a trigger number out of order ( 'syn-lost-draining' )
   Bit(31) : write a '1' to reset the status registers and counters
   
Offset: 0x4020  mask: 0xFFFFFFFF           name: L5gb_Seq_n_data_SlX1                  mode: R W   
   Bit(31..0) : contains the current packet sequence number for the incoming data packets. Beware that the sequence numbers for data-packets and those for command-packets are independent. 
   
Offset: 0x4024  mask: 0xFFFFFFFF           name: L5gb_Seq_n_Cmd_SlX1                   mode: R    
   Bit(31..0) : contains the current packet sequence number for command packets (send from FEROL side).

Offset: 0x4028  mask: 0xFFFFFFFF           name: L5gb_good_event_SlX1                  mode: R    
   Bit(31..0) : counts the number of correctly received event fragments. This is the number of fragments without SLINK-CRC error.
   
Offset: 0x402C  mask: 0xFFFFFFFF           name: L5gb_bad_event_SlX1                   mode: R    
   Bit(31..0) : count the number of bad events received, i.e. events with a SLINK-CRC error. 

Offset: 0x4030  mask: 0xFFFFFFFF           name: L5gb_bad_pack_received_SlX1           mode: R    
   Bit(31..0) : count the number of bad packets received. Bad packets are packets where an internal CRC error is detected (a CRC which is generated for the transfer of the packet over the optical link. This is different from the SLINK crc.)

Offset: 0x4034  mask: 0xFFFFFFFF           name: L5gb_Backpressure_SlX1                mode: R  
   Bit(31..0) : Counts how often a packet could not have been acknowledged since there was no free buffer available.
   
Offset: 0x4038  mask: 0xFFFFFFFF           name: L5gb_tot_pckt_rcv_SlX1                mode: R
   Bit(31..0) : counts the total number of packets (data or command) received (bad and good) 
               
Offset: 0x403C  mask: 0xFFFFFFFF           name: L5gb_received_packt_SlX1              mode: R
   Bit(31..0) : counts the number of good data packets received
   
Offset: 0x4040  mask: 0xFFFFFFFF           name: L5gb_trg_received_SlX0                mode: R
   Bit(31..0) : current trigger number received in the last packet   

4.1.5 General Functions 10Gb link


Offset: 0x5004  mask: 0xFFFFFFFF           name: SERDES_STATUS                         mode: R/W
   Bit(7..0): are registered bit not used (what you read is what you wrote)
   Bit(15..8) : RX_syn_status of the SERDES
   Bit(23..16): RX_patterndetect on SERDES
   Bit(27.24) RX_PLL_LOCKED (one for each 3.125 Gb link )
   Bit(31..28) not used 


Offset: 0x500C  mask: 0xFFFFFFFF           name: SERDES_RECONF                         mode: R/W
   This register is used to reconfigure the SERDES analog parameters.
   The default parameters should be used

Offset: 0x5010  mask: 0xFFFFFFFFFFFFFFFF   name: PACKETS_RECEIVED                      mode: R
   Counter the number of good packet received (64 bit)

Offset: 0x5018  mask: 0xFFFFFFFFFFFFFFFF   name: PACKETS_RECEIVED_BAD                  mode: R 
   Counter the number of bad packet received (64 bit)

Offset: 0x5020  mask: 0xFFFFFFFFFFFFFFFF   name: PACKETS_SENT                          mode: R 
   Counter the number of packet send (64 bit)
 

Offset: 0x5028  mask: 0x0000FFFFFFFFFFFF   name: MAC_SOURCE                            mode: R 
   The FEROL MAC address is kept in an EEPROM on each card. With this function, you can read the MAC address attributed to the card.

Offset: 0x5030  mask: 0xFFFFFFFF           name: IP_SOURCE                             mode: R/W
   The IP source address is setup by this function.
   Bit(31..0) IP_S(31..0).   

Offset: 0x5034  mask: 0xFFFFFFFF           name: IP_DEST                               mode: R/W
   The IP destination address is setup by this function.
   Bit(31..0)= IP_D(31..0).   The FEROL will execute an ARP to recover the corresponding MAC address.

Offset: 0x503C  mask: 0x00000001           name: RESET_COUNTERS                        mode: W
   bit(0) Reset internal status counter (active H)
   bit(31..1) reserved

4.1.5.1 FOR both FEDs

Offset: 0x5100  mask: 0xFFFFFFFFFFFFFFFF   name: TCP_STAT_TIMER                        mode: R
   Accumulate the Time used to average of time between Ack

Offset: 0x5108  mask: 0xFFFFFFFF           name: TCP_CONTROL_FEDS                      mode: R/W
   These bits are automatically reset
   
Offset: 0x510C  mask: 0x00000001           name:ENA_PAUSE_FRAME                        mode: R/W
   Bit(0) set to '1' will enable the Pause frame received to be executed
Offset: 0x510C  mask: 0x00000002          name:DHCP_REQUEST                            mode: R/W
   Bit(1) set to '1' will request a DHCP to be executed
Offset: 0x510C  mask: 0x00000004           name:PROBE_ARP                              mode: R/W
   Bit(2) set to '1' will request a Probe ARP to be executed  
Offset: 0x510C  mask: 0x00010000          name: ARP_REQUEST                            mode: R/W
   Bit(16) set to ‘1’ request a ARP to recover the destination MAC address

Offset: 0x5110  mask: 0x0000FFFFFFFFFFFF   name: MAC_DEST                              mode: R
   The MAC address destination answer on ARP IP destination
   Bit(74..0) MAC(74..0).

Offset: 0x5118  mask: 0xFFFFFFFF           name: IP_NETMASK                            mode: R/W
   Read and write the IP NETMASK of the 10Gbps link.(by default 0.0.0.0)

Offset: 0x511C mask: 0xFFFFFFFF            name: IP_GATEWAY                            mode: R/W
   Read and write the IP GATWAY of the 10Gbps link.(by default 0.0.0.0)   

   
Offset: 0x5120  mask: 0xFFFFFFFF           name: TCP_STATE_FEDS                        mode: R
   1 when connection established FED1
  Bit(31): 1 when the ARP request was executed correctly
Offset: 0x5124  mask: 0x80000000           name: TCP_ARP_REPLY_OK                      mode: R
   1 when the ARP request was successful

Offset: 0x5128  mask: 0xFFFFFFFF           name: PAUSE_FRAMES_COUNTER                  mode: R
   Counts how many pause frame  received by the FEROL (MOL)

Offset: 0x512C  mask: 0xFFFFFFFF           name: ARP_REQUEST_COUNTER                   mode: R
   Counts how many ARP REQUEST  received by the FEROL (MOL)
 

4.1.5.2 ARP probe


Offset: 0x5130  mask: 0xFFFFFFFF           name: ARP_MAC_CONFLICT                      mode: R
   Counts how many ARP(request/reply) were received with our MAC address (MAC address conflict detected)

Offset: 0x5134  mask: 0xFFFFFFFF           name: ARP_IP_CONFLICT                       mode: R
   Counts how many ARP(request/reply) were received with our IP address (IP address conflict detect)

Offset: 0x5138  mask: 0xFFFFFFFFFFFFFFFF   name: ARP_MAC_WITH_IP_CONFLICT              mode: R
   MAC address received from a ARP with our IP address. Should contain the MAC address of the conflicting device.

Offset: 0x5140  mask: 0x00000001           name: ARP_PROBE_DONE                        mode: R
   when '1', the ARP probe sequence is finished.

4.1.5.3 SFP+ 0

Offset: 0x6000  mask: 0xFFFFFFFF           name: SERDES_SETUP_FEROL                    mode: R/W
   This function setup the 10 Gb link 0
Offset: 0x4000  mask: 0x00000001           name: SERDES_UP                             mode: R/W
   Bit(0): Write '1' will execute a 10Gb/s Ethernet LINK UP. Read return all the time '0'. 
           This triggers a statemachine executing various power up procedures. These procedures take time (to be 
           determined by Dominique)
Offset: 0x6000 mask: 0x00000002            name: SERDES_STATUS                         mode: R
   Bit(1): Indicates if link (XAUI from FPGA to VITESSE) is up '1' or down '0'.
   Bit(2): Read only, return '0', write has no effect. The loop back function inside the SERDES is OFF. 
   Bit(3): Read only indicates the state of the GXB; ‘1’ GBX powerdown; ‘0’ GBX up.
   Bit(4): Read only indicates the state of the SERDES PLL: ‘1’ PLL unlocked; ‘0’ PLL is locked.
   Bit(5): Read only;’0’ non autonegociate.
   Bit(6): Read only;’0’IEEE standard PCS 64/66b: should be ‘0’

Offset: 0x6000 mask: 0x00000100            name: VT_SLITLOOP_N                         mode: R 
   Bit(8): read only; SLITLOOP, ‘1’ normal mode; No loop back inside the Vitesse chip.
   SLITLOOP, ‘1’ normal mode; ‘0’ loop back JK inside Vitesse chip.
   
   Bit(9): read only LASI Vitesse status on link A
   Bit(10): read only RX_alarm on link A
   Bit(11): read only TX alarm on link A
 
   Bit(15): RX_align of the link selected
   Bit(16): read only  SERDES TX digital reset (active H) of the link selected
   Bit(17): read only SERDES RX analog reset (active H) of the link selected
   Bit(18): read only SERDES RX digital reset (active H) of the link selected
   Bit(23..20): RX feq locked of the link selected
            
Offset: 0x6000 mask: 0x80000000            name: VT_RESET_N_L0                         mode: R/W
   Bit(31): Read only;This bit indicates if the Vitesse chip (10Gb/s eth link) is reset '0' or not reset '1'. 
   VSC reset (active low). Reset the Vitesse chip connected to the link used. The Vitesse is all the time reset.
 
Offset: 0x6004  mask: 0xFFFFFFFF           name: MDIO_LINK10GB_L0                      mode: R/W
   This function is used to access the Vitesse internal registers (read and write) via the MDIO bus.
   Read access : return the value requested
      Bit 15..0 the register value pointed by the request
      Bit 16 if ‘1’ indicate the rad request is executed (data is valid)
      If ‘0’, you should loop until it is ‘1’
   Write access:
      Bit(15..0): data you want to write
      Bit (17.16):  TA should be ‘10’ for a write request and any value is a read access request
      Bit(22..18): device address (see table 37 in page 93 VSC8486 datasheet)
      Bit(27..23) : ‘00000’ address component.
      Bit(29..28): 00 set the address register; 01 write data; 11 read data; 10 read data + address incrementation
      Bit(31..30) : 00
   For read and write accesses, you can poll the register to check the end of the previous access, bit 16 should change to '1'.
   An access takes 160 us.
 
Offset: 0x6008  mask: 0x00010000           name: MDIO_LINK10GB_POLL_L0                 mode: R
   Poll on this bit until it is '1' after a change of the Vitesse internal registers with the Write bits.
   An access takes 160 us.
   

4.1.5.4 SFP+ 1

Offset: 0x7000  mask: 0xFFFFFFFF           name: SERDES_SETUP_FEROL                    mode: R/W
   This function setup the 10 Gb link 0
Offset: 0x7000  mask: 0x00000001  name: SERDES_UP                                      mode: R/W
   Bit(0): Write '1' will execute a 10Gb/s Ethernet LINK UP. Read return all the time '0'. 
           This triggers a statemachine executing various power up procedures. These procedures take time (to be 
           determined by Dominique)
Offset: 0x4000 mask: 0x00000002            name: SERDES_STATUS                         mode: R
   Bit(1): Indicates if link (XAUI from FPGA to VITESSE) is up '1' or down '0'.
   Bit(2): Read only, return '0', write has no effect. The loop back function inside the SERDES is OFF. 
   Bit(3): Read only indicates the state of the GXB; ‘1’ GBX powerdown; ‘0’ GBX up.
   Bit(4): Read only indicates the state of the SERDES PLL: ‘1’ PLL unlocked; ‘0’ PLL is locked.
   Bit(5): Read only;’0’ non autonegociate.
   Bit(6): Read only;’0’IEEE standard PCS 64/66b: should be ‘0’
 
Offset: 0x7000 mask: 0x00000100            name: VT_SLITLOOP_N                         mode: R
   Bit(8): read only; SLITLOOP, ‘1’ normal mode; No loop back inside the Vitesse chip. 
   SLITLOOP, ‘1’ normal mode; ‘0’ loop back JK inside Vitesse chip.
 
   Bit(9): read only LASI Vitesse status on link A
   Bit(10): read only RX_alarm on link A
   Bit(11): read only TX alarm on link A
 
   Bit(15): RX_align of the link selected
   Bit(16): read only  SERDES TX digital reset (active H) of the link selected
   Bit(17): read only SERDES RX analog reset (active H) of the link selected
   Bit(18): read only SERDES RX digital reset (active H) of the link selected
   Bit(23..20): RX feq locked of the link selected
 
Offset: 0x7000 mask: 0x80000000            name: VT_RESET_N_L1                          mode: R/W
   Bit(31): Read only;This bit indicates if the Vitesse chip (10Gb/s eth link) is reset '0' or not reset '1'. 
   VSC reset (active low). Reset the Vitesse chip connected to the link used. The Vitesse is all the time reset.
 
Offset: 0x7004  mask: 0xFFFFFFFF           name: MDIO_LINK10GB_L1                       mode: R/W
   This function is used to access the Vitesse internal registers (read and write) via the MDIO bus.
   Read access : return the value requested
      Bit 15..0 the register value pointed by the request
      Bit 16 if ‘1’ indicate the rad request is executed (data is valid)
      If ‘0’, you should loop until it is ‘1’
   Write access:
      Bit(15..0): data you want to write
      Bit (17.16):  TA should be ‘10’ for a write request and any value is a read access request
      Bit(22..18): device address (see table 37 in page 93 VSC8486 datasheet)
      Bit(27..23) : ‘00000’ address component.
      Bit(29..28): 00 set the address register; 01 write data; 11 read data; 10 read data + address incrementation
      Bit(31..30) : 00
   For read and write accesses, you can poll the register to check the end of the previous access, bit 16 should change to '1'.
   An access takes 160 us.
 
Offset: 0x7008  mask: 0x00010000           name: MDIO_LINK10GB_POLL_L1                 mode: R
   Poll on this bit until it is '1' after a change of the Vitesse internal registers with the Write bits.
   An access takes 160 us.

4.1.5.5 TCP STREAM 0

 
Offset: 0x8000  mask: 0x00080000           name: TCP_OPEN_FED0                         mode: R/W
   Bit(0)  request an open connection for FED0
   request an open connection for FED0
Offset: 0x8000  mask: 0x00100000           name: TCP_RESET_FED0                        mode: R/W
   Bit(1) request a reset connection for FED0
   reset TCP connection to FED0
   
Offset: 0x8004  mask: 0xFFFFFFFF           name: TCP_STAT_ACK_COUNT_FED0               mode: R
   Return the number of Ethternet acks received since last Reset_Counter   
   
Offset: 0x8008  mask: 0xFFFFFFFF           name: TCP_STAT_ACK_DELAY_FED0               mode: R
   Return the time between the two last Ethternet acks (should be div 156.25 for uS)   
    
Offset: 0x8010  mask: 0xFFFFFFFF           name: TCP_CONFIGURATION_FED0                mode: R/W
   Bit 15..0 will setup the TCP window used for the FEROL source port.
   Bit 16: if set the TCP PUSH flag will be set in each packet
   Bit 17: this bit is RESERVED
   Bit 18: if set the no_delay will be used in the TCP state machine (see TCP detail)
   Bit 19: if set the Fast retransmit will be disabled in the TCP state machine
   Bit 20: if set the TIMER_STOP is disable on TCP state machine (state “RETRANS”)
   Other bits are reserved 

Offset: 0x8014  mask: 0xFFFFFFFF           name: TCP_OPTIONS_MSS_SCALE_FED0            mode: R/W
   Bit (15..0) : setup the Maximum Segment Size 
   Bit (31..16): setup the scale option 2)

Offset: 0x8018  mask: 0xFFFFFFFF           name: TCP_OPTION_TIMESTAMP_FED0             mode: R/W
   Not used

Offset: 0x801C  mask: 0xFFFFFFFF           name: TCP_OPTION_TIMESTAMP_REPLY_FED0       mode: R/W
   Not used

Offset: 0x8020  mask: 0xFFFFFFFF           name: TCP_CWND_FED0                         mode: R/W
   Bit(31..0) : setup the congestion window (CWND) (see TCP detail)

Offset: 0x8024  mask: 0xFFFFFFFF           name: TCP_TIMER_RTT_FED0                    mode: R/W
   Bit(31..0) : setup the RTT timer value(see TCP detail)
 
Offset: 0x8028  mask: 0xFFFFFFFF           name: TCP_TIMER_RTT_SYN_FED0                mode: R/W
   Bit(31..0) : setup the RTT timer value for synchronisation only (see TCP detail)

Offset: 0x802C  mask: 0xFFFFFFFF           name: TCP_TIMER_PERSIST_FED0                mode: R/W
   Bit(31..0) : setup the Persist timer value (see TCP detail)

Offset: 0x8030  mask: 0xFFFFFFFF           name: TCP_REXMTTHRESH_FED0                  mode: R/W
   Bit(15..0) : setup the maximum number of packet retrans before fast retrans  (see TCP detail)

Offset: 0x8034  mask: 0xFFFFFFFF           name: TCP_REXMTCWND_SHIFT_FED0              mode: R/W
   Bit(31..0) : value of shift RTT timer in congestion mode (see TCP detail)

Offset: 0x8038  mask: 0xFFFFFFFF           name: TCP_OPTION_MSS_REPLY_FED0             mode: R
   Bit(31..0) : value of the MSS (Maximum Segment Size) received from the PC during the stream opening. (see TCP detail)

Offset: 0x8040  mask: 0xFFFF0000           name: TCP_SOURCE_PORT_FED0                  mode: R/W
   This function setup the source port used for the TCP connection for FED0-stream

Offset: 0x8040  mask: 0x0000FFFF           name: TCP_DESTINATION_PORT_FED0             mode: R/W
   This function setup the destination ports used for the TCP connection for FED0-stream   
   
Offset: 0x8044  mask: 0xFFFFFFFF           name: LOSS_EMU_CONFIG_FED0                  mode: W
   This function has a mean for read and another for write (loss packet for FED0):
   Write:
      Bit 15..0 : set the threshold for the loss packet (compare to RND)
      Bit 31..16: set the seed for the pseudo RND number
   Read:
      Return the number of packet lost (volontary loss packet)   
   
Offset: 0x8048  mask: 0xFFFFFFFF           name: LOSS_EMU_ENABLE_FED0                  mode: W
   This function is used to simulate/introduce errors
   Bit (1) enable the TCP loss packet on FED 0
    
Offset: 0x804C  mask: 0xFFFFFFFF           name: TCP_STAT_ACK_DELAY_MAX_FED0           mode: R
   Maximum number of clocks (156.25 MHz) between two received ACK on STREAM0   
   
   
Offset: 0x8100  mask: 0xFFFFFFFF           name: GEN_TRIGGER_CONTROL_FED0              mode: W/R
   Bit(0): write a ‘1’ will generate one trigger
   Bit(1): set to 1: trigger will be generated in loop (should be set before or in the same time that bit (4)
   Bit(2): Set to 1 will stop the loop mode
   Bit(3): set to 1, the event length should be specify by offset 0x8330 and trigger generated by bit(0) of this offset (mode loop can be used).  Set to 0, the event length is specify by the descriptor wrote in the offset 0x8334, and only mode loop can be used.
   Bit(4): write a one will start the functionality of the event generator, this be should be set the last, when all other bits are set.
   Bit(5): write a ‘1’ will reset the RND memory.

Offset: 0x8108  mask: 0xFFFFFFFFFFFFFFFF   name: GEN_EVENT_NUMBER_FED0                 mode: W/R
   Bit(23..0) : set the first event number generated, the other will be incremented starting from this one. Other bits are set to '0' (63..24)
   Bit(63..0) : only in read mode. Event counter only the lower 24 bits are used to build the event header.

Offset: 0x8110  mask: 0xFFFFFFFF           name: GEN_FED_SOURCE_BX_FED0                mode: R/W
   Bit(11..0) : FED source number used to generate event fragment
   Bit(27..16): BX  number used to generate event fragment

Offset: 0x8114  mask: 0xFFFFFFFF           name: GEN_EVENT_LENGTH_FED0                 mode: R/W
   Bit(23..0) event length used to generate event fragment (in bytes)

Offset: 0x8118  mask: 0xFFFFFFFF           name: GEN_RND_MEMORY_FED0                   mode: R/W
   Bit(15..0): word count used to generate the event (in 64-bit word)
   Bit(31..16) the time before starting the next trigger(50MHz)
   This function can write up to 1024 values .The generator will loop over these values to generate event fragments (as a distribution)

Offset: 0x811C  mask: 0xFFFFFFFF           name: GEN_ERROR_GEN_FED0                    mode: W
   Bit(0) : write 1 generate a CRC error in the generated fragment 
   Bit(1): write 1 generate one bit error in the fragment payload
   These bit haven’t to be reset 

Offset: 0x8120  mask: 0xFFFFFFFFFFFFFFFF   name: BACK_PRESSURE_FED0                    mode: R
   64-bit counter ;clocked when the event generator are backpressured

Offset: 0x8128  mask: 0xFFFFFFFF           name: BIFI_USED_FED0                        mode: R
   Number of words used in the BIFI memory

Offset: 0x8130 mask: 0xFFFFFFFFFFFFFFFF    name: BACK_PRESSURE_BIFI_FED0               mode: R
   64-bit counter ;clocked when the BIFI memory is almost_FULL

Offset: 0x8138  mask: 0xFFFFFFFF           name: BIFI_USED_MAX_FED0                    mode: R
   32-bit counter ; return the maximum of used space in BIFI memory (max is 507904 almost_Full)

Offset: 0x8140  mask: 0xFFFFFFFFFFFFFFFF   name: BACK_PRESSURE_PERSIST_FED0            mode: R
   64-bit counter ; return the number clock when Backpressure and Persist STATE (in TCP logic)
 
Offset: 0x8200  mask: 0xFFFFFFFF           name: TCP_STAT_RTT_COUNTER_FED0             mode: R
   Number of RTT timeouts FED0 (see TCP details)
 
Offset: 0x8204  mask: 0x0000FFFF           name: TCP_STAT_CONNATTEMPT_FED0             mode: R
   number of connection attempt FED0 (see TCP details)

Offset: 0x8204  mask: 0xFFFF0000           name: TCP_STAT_CONNREFUSED_FED0             mode: R
   number of connection refused FED0 (see TCP details)

Offset: 0x8208  mask: 0x0000FFFF           name: TCP_STAT_CONNRST_FED0                 mode: R
   number of connection reset  FED0 (see TCP details)

Offset: 0x8208  mask: 0xFFFF0000           name: TCP_STAT_SNDPROBE_FED0                mode: R
   number of window probe sent FED0 (see TCP details)

Offset: 0x820C  mask: 0xFFFFFFFF           name: TCP_STAT_SNDPACK_FED0                 mode: R
   Number of packet sent FED0 (see TCP details)

Offset: 0x8210  mask: 0xFFFFFFFF           name: TCP_STAT_SNDREXMITPACK_FED0           mode: R
   Number of packet retransmitted  FED0 (see TCP details)

Offset: 0x8214  mask: 0xFFFFFFFF           name: TCP_STAT_RCVDUPACK_FED0               mode: R
   Number of received Duplicate Acknowledge FED0 (see TCP details)

Offset: 0x8218  mask: 0xFFFFFFFF           name: TCP_STAT_FASTRETRANSMIT_FED0          mode: R
   Number of fast retransmit FED0 (see TCP details)

Offset: 0x821C  mask: 0xFFFFFFFF           name: TCP_STAT_MEASURE_RTT_COUNT_FED0       mode: R
   Number of time we enter in Measure RTT state FED0 (see TCP details)

Offset: 0x8220  mask: 0xFFFFFFFF           name: TCP_STAT_RCVACKTOOMUCH_FED0           mode: R
   Number of received ack to much FED0 (see TCP details)

Offset: 0x8224  mask: 0xFFFFFFFF           name: TCP_STAT_SEG_DROP_AFTER_ACK_FED0      mode: R
   Number of dropped after ack FED0 (see TCP details)

Offset: 0x8228  mask: 0xFFFFFFFF           name: TCP_STAT_SEG_DROP_FED0                mode: R
   Number of segment dropped  FED0 (see TCP details)

Offset: 0x822C  mask: 0xFFFFFFFF           name: TCP_STAT_SEG_DROP_WITH_RST_FED0       mode: R
   Number of segment dropped with reset  FED0 (see TCP details)

Offset: 0x8230  mask: 0xFFFFFFFF           name: TCP_STAT_PERSIST_EXITED_FED0          mode: R
   Number Persist state exit  FED0 (see TCP details)

Offset: 0x8234  mask: 0xFFFFFFFF           name: TCP_STAT_PERSIST_FED0                 mode: R
   Number of persist state FED0 (see TCP details)

Offset: 0x8238  mask: 0xFFFFFFFFFFFFFFFF   name: TCP_STAT_SNDBYTE_FED0                 mode: R
   Number of bytes sent  FED0 (see TCP details)

Offset: 0x8240  mask: 0xFFFFFFFFFFFFFFFF   name: TCP_STAT_SNDREXMITBYTE_FED0           mode: R
   Number of bytes retransmitted  FED0 (see TCP details)

Offset: 0x8248  mask: 0xFFFFFFFF           name: TCP_STAT_PERSIST_CLOSEDWND_FED0       mode: R
   Number of persist closed window(see TCP details)

Offset: 0x824C  mask: 0xFFFFFFFF           name: TCP_STAT_DUPACK_MAX_FED0              mode: R
   Maximum value of Duplicate ack received FED0 (see TCP details)

Offset: 0x8250  mask: 0xFFFFFFFF           name: TCP_STAT_WND_MAX_FED0                 mode: R
   Maximum value of WIN received FED0 (see TCP details)

Offset: 0x8254  mask: 0xFFFFFFFF           name: TCP_STAT_WND_MIN_FED0                 mode: R
   Minimum value of WIN received FED0 (see TCP details)

Offset: 0x8258  mask: 0xFFFFFFFF           name: TCP_STAT_MEASURE_RTT_MAX_FED0         mode: R
   Maximum of the RTT measure FED0 (see TCP details)

Offset: 0x825C  mask: 0xFFFFFFFF           name: TCP_STAT_MEASURE_RTT_MIN_FED0         mode: R
   Minimum of the RTT measure FED0 (see TCP details)

Offset: 0x8260  mask: 0xFFFFFFFFFFFFFFFF   name: TCP_STAT_MEASURE_RTT_SUM_FED0         mode: R
   Number of RTT measure FED0 (see TCP details)

Offset: 0x8268  mask: 0xFFFFFFFF           name: TCP_STAT_CURRENT_WND_FED0             mode: R
   Latest WND value received FED0 (see TCP details)

Offset: 0x826C  mask: 0xFFFFFFFF           name: TCP_STAT_PERSIST_ZEROWND_FED0         mode: R
   Number of Persist Win Zero FED0 (see TCP details)

Offset: 0x8270  mask: 0xFFFFFFFF           name: TCP_STAT_RTT_SHIFTS_MAX_FED0          mode: R
   Max value of the Shift RTT FED0 (see TCP details)

Offset: 0x8274  mask: 0xFFFFFFFF           name: TCP_STAT_MEASURE_RTT_FED0             mode: R
   Measured RTT value in clock cycles FED0 (see TCP details)

Offset: 0x8278  mask: 0x00000004           name: TCP_CONNECTION_ESTABLISHED_FED0       mode: R
   Bit(0):  1 when connection reset  FED0
   Bit(1):  1 when connection request sync FED0
   Bit(2):  1 when connection established FED0

 

4.1.5.6 TCP STREAM 1

 
Offset: 0x9000  mask: 0x00080000           name: TCP_OPEN_FED1                         mode: R/W
   Bit(0)  request an open connection for FED1
   request an open connection for FED1
Offset: 0x9000  mask: 0x00100000           name: TCP_RESET_FED1                        mode: R/W
   Bit(1) request a reset connection for FED1
   reset TCP connection to FED1

Offset: 0x9004  mask: 0xFFFFFFFF           name: TCP_STAT_ACK_COUNT_FED1               mode: R
   Return the number of Ethternet acks received since last Reset_Counter   
   
Offset: 0x9008  mask: 0xFFFFFFFF           name: TCP_STAT_ACK_DELAY_FED1               mode: R
   Return the time between the two last Ethternet acks (should be div 156.25 for uS)   
 
Offset: 0x9010  mask: 0xFFFFFFFF           name: TCP_CONFIGURATION_FED1                mode: R/W
   Bit 15..0 will setup the TCP window used for the FEROL source port.
   Bit 16: if set the TCP PUSH flag will be set in each packet
   Bit 17: if set the RTT measure will be executed in the TCP state machine
   Bit 18: if set the no_delay will be used in the TCP state machine (see TCP detail)
   Bit 19: if set the Fast retransmit will be execute in the TCP state machine
   Bit 20: if set the TIMER_STOP is disable on TCP state machine (state “RETRANS”)
   Other bits are reserved 

Offset: 0x9014  mask: 0xFFFFFFFF           name: TCP_OPTIONS_MSS_SCALE_FED1            mode: R/W
   Bit (15..0) : setup the Maximum Size Segment
   Bit (31..16): setup the scale option 2)

Offset: 0x9018  mask: 0xFFFFFFFF           name: TCP_OPTION_TIMESTAMP_FED1             mode: R/W
   Not used

Offset: 0x901C  mask: 0xFFFFFFFF           name: TCP_OPTION_TIMESTAMP_REPLY_FED1       mode: R/W
   Not used
 
Offset: 0x9020  mask: 0xFFFFFFFF           name: TCP_CWND_FED1                         mode: R/W
   Bit(31..0) : setup the congestion window (CWND) (see TCP detail)

Offset: 0x9024  mask: 0xFFFFFFFF           name: TCP_TIMER_RTT_FED1                    mode: R/W
   Bit(31..0) : setup the RTT timer value(see TCP detail)
 
Offset: 0x9028  mask: 0xFFFFFFFF           name: TCP_TIMER_RTT_SYN_FED1                mode: R/W
   Bit(31..0) : setup the RTT timer value for synchronization only (see TCP detail)

Offset: 0x902C  mask: 0xFFFFFFFF           name: TCP_TIMER_PERSIST_FED1                mode: R/W
   Bit(31..0) : setup the Persist timer value (see TCP detail)

Offset: 0x9030  mask: 0xFFFFFFFF           name: TCP_REXMTTHRESH_FED1                  mode: R/W
   Bit(15..0) : setup the maximum number of packet retrans before fast retrans  (see TCP detail)

Offset: 0x9034  mask: 0xFFFFFFFF           name: TCP_REXMTCWND_SHIFT_FED1              mode: R/W
   Bit(31..0) : value of shift RTT timer in congestion mode (see TCP detail)

Offset: 0x9038  mask: 0xFFFFFFFF           name: TCP_OPTION_MSS_REPLY_FED1             mode: R
   Bit(31..0) : value of the MSS (Maximum Segment Size) received from the PC during the stream opening. (see TCP detail)
   
Offset: 0x9040  mask: 0xFFFF0000           name: TCP_SOURCE_PORT_FED1                  mode: R/W
   This function setup the source port used for the TCP connection for FED1-stream

Offset: 0x9040  mask: 0x0000FFFF           name: TCP_DESTINATION_PORT_FED1             mode: R/W
   This function setup the destination port used for the TCP connection for FED1-stream

Offset: 0x9044  mask: 0xFFFFFFFF           name: LOSS_EMU_CONFIG_FED1                  mode: W
   This function has a mean for read and another for write (loss packet for FED1):
   Write
      Bit 15..0 : set the threshold for the loss packet (compare to RND)
      Bit 31..16: set the seed for the pseudo RND number
   Read:
      Return the number of packet lost (volontary loss packet)
      
Offset: 0x9048  mask: 0xFFFFFFFF           name: LOSS_EMU_ENABLE_FED1                  mode: W
   This function is used to simulate/introduce errors
   Bit (2) enable the TCP loss packet on FED 1
      
Offset: 0x904C  mask: 0xFFFFFFFF           name: TCP_STAT_ACK_DELAY_MAX_FED1           mode: R
   Maximum number of clocks (156.25 MHz) between two received ACK on STREAM1
   
Offset: 0x9100  mask: 0xFFFFFFFF           name: GEN_TRIGGER_CONTROL_FED1              mode: W/R
   Bit(0): write a ‘1’ will generate one trigger
   Bit(1): set to 1: trigger will be generated in loop (should be set before or in the same time that bit (4)
   Bit(2): Set to 1 will stop the loop mode
   Bit(3): set to 1, the event length should be specify by offset 0x9330 and trigger generated by bit(0) of this offset (mode loop can be used).  Set to 0, the event length is specify by the descriptor wrote in the offset 0x9334, and only mode loop can be used.
   Bit(4): write a one will start the functionality of the event generator, this be should be set the last, when all other bits are set.
   Bit(5): write a ‘1’ will reset the RND memory.

Offset: 0x9108  mask: 0xFFFFFFFFFFFFFFFF   name: GEN_EVENT_NUMBER_FED1                 mode: W/R
   Bit(23..0) : set the first event number generated, the other will be incremented starting from this one. Other bits are set to '0' (63..24)
   Bit(63..0) : only in read mode. Event counter only the lower 24 bits are used to build the event header.

Offset: 0x9110  mask: 0xFFFFFFFF           name: GEN_FED_SOURCE_BX_FED1                mode: R/W
   Bit(11..0) : FED source number used to generate event fragment
   Bit(27..16): BX  number used to generate event fragment

Offset: 0x9114  mask: 0xFFFFFFFF           name: GEN_EVENT_LENGTH_FED1                 mode: R/W
   Bit(23..0) event length used to generate event fragment (in bytes)

Offset: 0x9118  mask: 0xFFFFFFFF           name: GEN_RND_MEMORY_FED1                   mode: R/W
   Bit(15..0): word count used to generate the event (in 64-bit word)
   Bit(31..16) the time before starting the next trigger(50MHz)
   This function can write up to 1024 values .The generator will loop over these values to generate event fragments (as a distribution)

Offset: 0x911C  mask: 0xFFFFFFFF           name: GEN_ERROR_GEN_FED1                    mode: W
   Bit(0) : write 1 generate a CRC error in the generated fragment 
   Bit(1): write 1 generate one bit error in the fragment payload
   These bit haven’t to be reset 

Offset: 0x9120  mask: 0xFFFFFFFFFFFFFFFF   name: BACK_PRESSURE_FED1                    mode: R
   64-bit counter ;clocked when the event generator are backpressured

Offset: 0x9128  mask: 0xFFFFFFFF           name: BIFI_USED_FED1                        mode: R
   Number of words used in the BIFI memory
 
Offset: 0x9130  mask: 0xFFFFFFFFFFFFFFFF   name: BACK_PRESSURE_BIFI_FED1               mode: R
   64-bit counter ; clocked when the BIFI memory is almost_FULL 
 
Offset: 0x9138  mask: 0xFFFFFFFF           name: BIFI_USED_MAX_FED1                    mode: R
   32-bit counter ; return the maximum of used used in BIFI memory (max is 507904 almost_Full)
 
Offset: 0x9140  mask: 0xFFFFFFFFFFFFFFFF   name: BACK_PRESSURE_PERSIST_FED1            mode: R
   64-bit counter ; return the number clock when Backpressure and Persist STATE (in TCP logic)
 
Offset: 0x9200  mask: 0xFFFFFFFF           name: TCP_STAT_RTT_COUNTER_FED1             mode: R
   Number of RTT timeouts FED (see TCP details)
 
Offset: 0x9204  mask: 0x0000FFFF           name: TCP_STAT_CONNATTEMPT_FED1             mode: R
   number of connection attempt FED1 (see TCP details)

Offset: 0x9204  mask: 0xFFFF0000           name: TCP_STAT_CONNREFUSED_FED1             mode: R
   number of connection refused FED1 (see TCP details)

Offset: 0x9208  mask: 0x0000FFFF           name: TCP_STAT_CONNRST_FED1                 mode: R
   number of connection reset  FED1 (see TCP details)

Offset: 0x9208  mask: 0xFFFF0000           name: TCP_STAT_SNDPROBE_FED1                mode: R
    number of window probe sent FED1 (see TCP details)

Offset: 0x920C  mask: 0xFFFFFFFF           name: TCP_STAT_SNDPACK_FED1                 mode: R
   Number of packet sent FED1 (see TCP details)

Offset: 0x9210  mask: 0xFFFFFFFF           name: TCP_STAT_SNDREXMITPACK_FED1           mode: R
   Number of packet retransmitted  FED1 (see TCP details)

Offset: 0x9214  mask: 0xFFFFFFFF           name: TCP_STAT_RCVDUPACK_FED1               mode: R
   Number of received Duplicate Acknowledge FED1 (see TCP details)

Offset: 0x9218  mask: 0xFFFFFFFF           name: TCP_STAT_FASTRETRANSMIT_FED1          mode: R
   Number of fast retransmit FED1 (see TCP details)

Offset: 0x921C  mask: 0xFFFFFFFF           name: TCP_STAT_MEASURE_RTT_COUNT_FED1       mode: R
   Number of time we enter in Measure RTT state FED1 (see TCP details)

Offset: 0x9220  mask: 0xFFFFFFFF           name: TCP_STAT_RCVACKTOOMUCH_FED1           mode: R
   Number of received ack to much FED1 (see TCP details)

Offset: 0x9224  mask: 0xFFFFFFFF           name: TCP_STAT_SEG_DROP_AFTER_ACK_FED1      mode: R
   Number of dropped after ack FED1 (see TCP details)

Offset: 0x9228  mask: 0xFFFFFFFF           name: TCP_STAT_SEG_DROP_FED1                mode: R
   Number of segment dropped  FED1 (see TCP details)

Offset: 0x922C  mask: 0xFFFFFFFF           name: TCP_STAT_SEG_DROP_WITH_RST_FED1       mode: R
   Number of segment dropped with reset  FED1 (see TCP details)

Offset: 0x9230  mask: 0xFFFFFFFF           name: TCP_STAT_PERSIST_EXITED_FED1          mode: R
   Number Persist state exit  FED1 (see TCP details)

Offset: 0x9234  mask: 0xFFFFFFFF           name: TCP_STAT_PERSIST_FED1                 mode: R
   Number of persist state FED1 (see TCP details)

Offset: 0x9238  mask: 0xFFFFFFFFFFFFFFFF   name: TCP_STAT_SNDBYTE_FED1                 mode: R
   Number of bytes sent  FED1 (see TCP details)

Offset: 0x9240  mask: 0xFFFFFFFFFFFFFFFF   name: TCP_STAT_SNDREXMITBYTE_FED1           mode: R
   Number of bytes retransmitted  FED1 (see TCP details)

Offset: 0x9248  mask: 0xFFFFFFFF           name: TCP_STAT_PERSIST_CLOSEDWND_FED1       mode: R
   Number of persist closed window(see TCP details)

Offset: 0x924C  mask: 0xFFFFFFFF           name: TCP_STAT_DUPACK_MAX_FED1              mode: R
   Maximum value of Duplicate ack received FED1 (see TCP details)

Offset: 0x9250  mask: 0xFFFFFFFF           name: TCP_STAT_WND_MAX_FED1                 mode: R
   Maximum value of WIN received FED1 (see TCP details)

Offset: 0x9254  mask: 0xFFFFFFFF           name: TCP_STAT_WND_MIN_FED1                 mode: R
   Minimum value of WIN received FED1 (see TCP details)

Offset: 0x9258  mask: 0xFFFFFFFF           name: TCP_STAT_MEASURE_RTT_MAX_FED1         mode: R
   Maximum of the RTT measure FED1 (see TCP details)

Offset: 0x925C  mask: 0xFFFFFFFF           name: TCP_STAT_MEASURE_RTT_MIN_FED1         mode: R
   Minimum of the RTT measure FED1 (see TCP details)

Offset: 0x9260  mask: 0xFFFFFFFFFFFFFFFF   name: TCP_STAT_MEASURE_RTT_SUM_FED1         mode: R
   Number of RTT measure FED1 (see TCP details)

Offset: 0x9268  mask: 0xFFFFFFFF           name: TCP_STAT_CURRENT_WND_FED1             mode: R
   Latest WND value received FED1 (see TCP details)

Offset: 0x926C  mask: 0xFFFFFFFF           name: TCP_STAT_PERSIST_ZEROWND_FED1         mode: R
   Number of Persist Win Zero FED1 (see TCP details)

Offset: 0x9270  mask: 0xFFFFFFFF           name: TCP_STAT_RTT_SHIFTS_MAX_FED1          mode: R
   Max value of the Shift RTT FED1 (see TCP details)

Offset: 0x9274  mask: 0xFFFFFFFF           name: TCP_STAT_MEASURE_RTT_FED1             mode: R
   Measured RTT value in clock cycles FED1 (see TCP details)

Offset: 0x9278  mask: 0x00040000           name: TCP_CONNECTION_ESTABLISHED_FED1       mode: R
   Bit(0): 1 when connection reset  FED1
   Bit(1): 1 when connection request sync FED1
   Bit(2): 1 when connection established FED1
   

--### Memory

   
Offset: 0x10000  mask: 0xFFFFFFFF          name: Memory_QDR                            mode: R/W    BAR: 1
   With this offset (from 0x10000 to 0x1FFFFF)  the memory is accessed by block of 64kbytes. To change the block (high memory address), you should write the memory address xx..16 to the offset 0x10 (BA0) bit xx..16.
   Memory access in single access mode, the higer part of the address is specified by the offset 0x10 BA(0)
   
Offset: 0x20000  mask: 0xFFFFFFFF          name: Memory_DDR                            mode: R/W    BAR: 1
   With this offset (from 0x20000 to 0x2FFFFF)  the memory is accessed by block of 64kbytes. To change the block (high memory address), you should write the memory address xx..16 to the offset 0x14 (BA0) bit xx..16.
   Memory access in single access mode, the higer part of the address is specified by the offset 0x14 BA(0) 
 
Offset: 0xF0000  mask: 0xFFFFFFFF          name: Memory_MAX                            mode: R/W    BAR: 1
 

4.1.6 JTAG access


Offset: 0x8090  mask: 0xFFFFFFFF           name: JTAG_TDE                              mode: R/W
   Write to this register the bit available to be shifted in a JTAG access. A bit is care for the shift when it is set to ‘1’. The bit available should start from the lower bit (bit 0 ) without hole. As soon as a bit is ‘0’ the bits upper will be ignored. This register should not be reloaded at each time if it doesn’t change.

Offset: 0x8094  mask: 0xFFFFFFFF           name: JTAG_TDI                              mode: R/W
   This register loads TDI bits to be shifted in a JTAG access. A write access to this register will start a JTAG shift access. Other JTAG register should load before. 

Offset: 0x8098  mask: 0xFFFFFFFF           name: JTAG_TMS                              mode: R/W
   This register loads the TMS bits to be shifted during a JTAG access. This register should not be reloaded at each time if it doesn’t change.

Offset: 0x809C  mask: 0xFFFFFFFF           name: JTAG_TDO                              mode: R
   This register return the TDO bit shifted during a JTAG access. When a JTAG access is initiated by JTAG_TDI function (offset 0x8094). The access to JTAG_TDO will generate a PCI retry if the software try to read it and the JTAG access is not finished.

4.2 Default values

Here are described some default values for the TCP settings. These values will be later updated to the more optimal values depending of the number of aggregated streams.

Note: Some values are in HEXADECIMAL, some values are in DECIMAL.

  • TCP_CONFIGURATION_FEDn = 0x00004000
  • TCP_OPTIONS_MSS_SCALE_FEDn = 0x00012300
  • TCP_CWND_FEDn = 300000
  • TCP_TIMER_RTT_FEDn = 312500
  • TCP_TIMER_RTT_SYN_FEDn = 312500000
  • TCP_TIMER_PERSIST_FEDn = 625000
  • TCP_REXMTTHRESH_FEDn = 3
  • TCP_REXMTCWND_SHIFT_FEDn = 6
These registers are not used:
  • TCP_OPTION_TIMESTAMP_FED0
  • TCP_OPTION_TIMESTAMP_REPLY_FED0

4.3 Calculations

Some of the registers may be recalculated to use a more meaningful units (e.g. percentage or microseconds).

Values:

PACK_REXMIT_FEDn [%]
= 100.0 * TCP_STAT_SNDREXMITPACK_FEDn / TCP_STAT_SNDPACK_FEDn
RTT_FEDn [us]
= TCP_STAT_MEASURE_RTT_FEDn / 156.25
RTT_MAX_FEDn [us]
= TCP_STAT_MEASURE_RTT_MAX_FEDn / 156.25
RTT_MIN_FEDn [us]
= TCP_STAT_MEASURE_RTT_MIN_FEDn / 156.25
AVG_RTT_FEDn [us]
= TCP_STAT_MEASURE_RTT_SUM_FEDn / TCP_STAT_MEASURE_RTT_COUNT_FEDn / 156.25
ACK_DELAY_MAX_FEDn [us]
= TCP_STAT_ACK_DELAY_MAX_FEDn / 156.25
ACK_DELAY_FEDn [us]
= TCP_STAT_ACK_DELAY_FEDn / 156.25
AVG_ACK_DELAYn
= TCP_STAT_TIMER / TCP_STAT_ACK_COUNT_FEDn / 156.25
BIFI_FEDn [%]
= 100.0 * BIFI_USED_FEDn / 507904
BIFI_MAX_FEDn [%]
= 100.0 * BIFI_USED_MAX_FEDn / 507904

The following equation is used to set the event generator delay:

 \begin{displaymath} GenDelay = \frac{\displaystyle\frac{1000000}{Freq[kHz]} - \frac{EventSize[Bytes] * 8}{64*0.15625}}{20} \end{displaymath}

The time is calculated in [nsec], then it is divided by 20 becuse of 20ns units due to a 50 MHz clock used to generate the delay.

4.4 Procedure

In this procedure the x in the function name will replace the 0 and 1 for the FED number. The procedure to use the 10Gb link is the following: To setup the FEROL/MOL card, you sould follow the description access register below: There are some minor differences between FEROL and MOL.

  1. Reset the board
    • The general reset is done when you write '1' to bit 17 of the function "CONTROL".
  2. Release Vitesse chip reset *Write 0x180 to the function "SERDES_SETUP_FEROL"
  3. Read the functions "MDIO_LINK10GB_A" (poll bit 16 to check that the logic is in IDLE state)
  4. Init the FPGA SERDES *Write 0x1 to the function "SERDES_SETUP_FEROL" *you can poll the bit 1 of the same function. A '1' is returned when the SERDES reset sequence is done.
  5. Check if the link is UP (optical part)
    • to do this: first set the address where to poll on MDIO, write 0x00060001 to functions "MDIO_LINK10GB_B" (poll bit 16 to check that the access is finished) second loop on the 2 following accesses: (a) request a read MDIO (write 0x30040000 to functions "MDIO_LINK10GB_B") (b) poll function "MDIO_LINK10GB_B" until bit 16 is '1' (read is executed) then the bit 2 should '1' (link Up ) if not goto to (a)
  6. Setup IP addresses, Port numbers, MAC of the card(later the MAC address will be on board for FEROL)
    • To do this execute the following functions with the appropriate values:
    • "MAC_SOURCE" (later this function will not be necessary and will be read only); "IP_SOURCE"; "IP_DEST"; "TCP_PORT_FEDx"
    • Other registers should be set (FPGA contains default values). The expert should specify these values (TCP parameters)
  7. Do an ARP
    • To execute an ARP to recover the MAC address of the destination, execute the following function "TCP_CONTROL_FEDS" where you set the bit 16 to '1'. You can poll the function "TCP_STATE_FEDS" bit 31 to verify that ARP request has received a reply. This bit should be '1' after a while. You can read the destination MAC address with the function "MAC_DEST"
  8. Open connections for one or two stream(s)
    • To open TCP connection of FED0 stream write a '1' to bit 17 function "TCP_CONTROL_FEDS"; for FED 1 stream write a '1' on bit 19 of the same function.
    • You can check the state of each stream with function "TCP_STATE_FEDS".
  9. Setup the data generators
    • First of all you may setup BX#, Evt# (see functions above). Three ways to generate data:
    • 1. You set a fragment size with function "GEN_EVENT_LENGTH_FEDx" and start the generator with function "GEN_TRIGGER_CONTROL_FEDx": write x18 follow by x19 for each trigger
    • 2. You setup the generator as above but write x1A to function "GEN_TRIGGER_CONTROL_FEDx", event will be generated one after the other.
    • 3. You want to generate event with time and size distribution, then you should first fill a FIFO with function (RND_memory_FEDx), you can write up to 1024 values (the FIFO can be reset with function "GEN_TRIGGER_CONTROL_FEDx" bit 5). And start the generator : write function "GEN_TRIGGER_CONTROL_FEDx" value x10.
    • To stop the generator write bit 3 of function "GEN_TRIGGER_CONTROL_FEDx".
  10. Now….it should work! If not Something is wrong somewhere....... but Where?
  11. Later, you can close the connection (done by a reset connection)
    • To close the connection , you should use the function "TCP_CONTROL_FEDS". Generator will be reset automatically in the case where you don't stop it(them).
  12. you can use the various functions to monitor the RUN.

4.5 High-level procedure for establishing a TCP connection (software part)

  1. Check for the valid IP configuration
    • Check if the IP_SOURCE is configured (is other than zero). if not raise an exception. The IP_SOURCE should have been configured before the TCP connection open is requested.
    • Check if the IP_NETMASK is configured (is other than zero). If not, then gateway is not used, skip the following check and continue with step 2.
    • If IP_NETMASK is non zero, check if the IP_GATEWAY is also non zero. If not, raise an exception with an explanation that "netmask is specified but gateway address is missing"
  2. Send an ARP Probe and wait for completion
  3. Start the continuous MAC/IP duplicate detection procedure
    • Check ARP_MAC_CONFLICT if is non zero. If yes, an exception or error message should be sent with an explanation "Duplicate MAC address conflict detected".
    • Check ARP_IP_CONFLICT if is non zero. If yes, an exception or error message should be sent with an explanation "Duplicate IP address conflict detected (MAC address of duplicate is: [read register ARP_MAC_WITH_IP_CONFLICT])". The register ARP_MAC_WITH_IP_CONFLICT is pointing to the MAC address of the conflicting device.
  4. Since this time the MAC/IP duplicate detection procedure should run forever in the background e.g. as part of the monitoring system. The hardware is checking the MAC and IP addresses continuously in the all received ARP packets and thus is able to detect the conflicts also passively without the need for periodical ARP probing.
  5. Continue only if no (IP or MAC) conflict was detected
  6. Set the DEST_IP register
  7. Send an ARP to recover the MAC addresses of the destination IP (and/or gateway IP) and wait for completion
  8. Open a TCP connection
  9. Check if the MTU is correctly set in the receiving PC:
    • Read TCP_OPTION_MSS_REPLY_FED0 and/or _FED1 register respectively and check if it is equal or greater than 8960. If not, raise an exception because the receiving PC is not properly configured (the MTU is not set to 9000). Note: MSS ~ MTU - 40. Therefore, the check is for 8960

4.6 TCP Details

4.6.1 Useful registers

The following text describes a few registers which monitor the health of the TCP connection:

4.6.1.1 Basic FEROL registers:

  • PACKETS_SENT
    • Number of sent packets. All packets which leave the FEROL are counted here (ARP, PING, sent and retransmitted TCP/IP pkts, dhcp, ...)
  • PACKETS_RECEIVED
    • Number of received packets
  • PACKETS_RECEIVED_BAD
    • Number of packets with an error (e.g. CRC error)

4.6.1.2 Basic TCP registers:

  • TCP_CONNECTION_ESTABLISHED
    • TCP connection was successfully established with the remote server
  • TCP_STAT_CONNATTEMPT
    • Counts the number of attempts for establishing a TCP connections (number of sent SYN packets)
  • TCP_STAT_CONNREFUSED
    • TCP connection was refused by the remote server (the number of received RST packets)
  • TCP_STAT_CONNRST
    • Remote server closed the TCP connection

  • TCP_STAT_SNDPACK
    • Only counting TCP packets sent but excluding the retransmitted packets.
  • TCP_STAT_SNDREXMITPACK
    • Number of retransmitted packets. (See a note bellow)

  • RTT
    • TCP RTT value
  • AVG_RTT
    • Average TCP RTT value

  • BIFI_USED
  • BIFI_USED_MAX
NOTE about retransmitted packets:
  • If there are no retransmissions (TCP_STAT_SNDREXMITPACK is not increasing), then TCP_STAT_SNDPACK is the number of packets successfully sent from client and received (acknowledged) by the remote server. If TCP_STAT_SNDREXMITPACK is increasing and TCP_STAT_SNDPACK is not, then the served might have crashed. For expert: Check if some packets are received (PACKETS_RECEIVED) or not.

4.6.1.3 Advanced TCP registers (requires deeper TCP knowledge):

  • TCP_STAT_PERSIST
    • Counts how many times FEROL entered persist state. (See a note bellow)
  • TCP_STAT_PERSIST_EXITED
    • Counts how many times FEROL exited persist state. (See a note bellow)
  • TCP_STAT_SNDPROBE
    • Number of probes sent during the persist state. (See a note bellow)
  • TCP_STAT_RCVDUPACK
    • Number of duplicate acknowledgement received. The result of persist state or some network error. (See a note bellow)

  • PAUSE_FRAMES_COUNTER
    • Number of pause frames received by the FEROL.
NOTE about FEROL TCP persist state:
  • A TCP persist state is an backpressure condition and is entered when the remote server socket buffers are full (e.g. when an application stops to read data). TCP is in the persist state when TCP_STAT_PERSIST is greater (by one) than TCP_STAT_PERSIST_EXITED. In the persist state TCP is sending a probe (see TCP_STAT_SND_PROBE) to the remote server in order to find out if the persist state sill persists or not (is asking can I send new data?). The remote server is supposed to reply and the replies are included in TCP_STAT_RCVDUPACK. Registers TCP_STAT_RCVDUPACK and TCP_STAT_SND_PROBE should increase with the same rate during persist state. If TCP_STAT_RCVDUPACK is not increasing and TCP_STAT_SND_PROBE is, the remote server might have crashed. For expert: Check if some packets are received (PACKETS_RECEIVED) or not.

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