FPGA Devices

Recent results suggest that the Virtex 6 and Spartan 6 generation has a smaller SEU cross section per configuration bit than earlier families; In the order of 50 to 500 times better than the earlier Virtex families. This result is supported by the following article from Xilinx and LANL engineers. The Virtex/Spartan 6 devices have variable thickness oxide for the processing and configuration memory transistors. The primary goal of this is to reduce static power dissipation of the configuration memory. The thick oxide transistors are much slower switching but leak far less. The thicker oxide will give better resistance to SEUs at the expense of total dose resistance.

The TID has been tested and results suggest resistance up to several hundred krads. Details are given in this talk at by J. Gebelein(KIP):

The Virtex7 series can be expected to perform even better than the Virtex 6 and Spartan 6 thanks to the built in scrubbing and ECC configuration memory. Until tested this remains, however, pure speculation.

Special thanks to: Matt Stettler(BNL)

Design methods

HEP Community forums

A Mailing list for Radiation Tolerant design techniques discussions is active: fpga-radtol@cern.ch. Jorgen Christiansen is the owner of the mailing list and you need to mail him to get added to the list.

-- MagnusHansen - 05-Oct-2011

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PDFpdf WFIFT_P11_Gebelein.pdf r1 manage 12394.8 K 2011-10-05 - 16:40 MagnusHansen An approach to system-wide fault tolerance for FPGAs
PDFpdf XILINX_radhard_quinn_nsrec_HPC_journal_paper.pdf r1 manage 8498.6 K 2011-10-05 - 16:39 MagnusHansen XILINX and LANL Virtex6/Spartan6 SEU test paper
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Topic revision: r2 - 2011-10-06 - MagnusHansen
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