SRS - Short User Guide

APV readout - Raw data mode (ADC mode) Front-end initialisation

The default power up values of the APV25 and ADC-Card registers do not allow correct operation so an initialization sequence has to be performed:

\\ setting ADC C/card registers default values WITH ADCCARD_PORT \\ write ADC C-CARD registers WRITE HYBRID_RST_N 0x00 \\ (addr 0x00) reset all APVs WRITE PWRDOWN_CH0 0x00 \\ (addr 0x01) power on master channels circuitry WRITE PWRDOWN_CH1 0x00 \\ (addr 0x02) power on slave channels circuitry WRITE EQ_LEVEL_0 0x00 \\ (addr 0x03) equalization set to 0 WRITE EQ_LEVEL_1 0x00 \\ (addr 0x04) equalization set to 0 WRITE TRGOUT_ENABLE 0x00 \\ (addr 0x05) when PLL is used disable trg out WRITE BCLK_ENABLE 0xFF \\ (addr 0x06) enable clock&trg outputs

WRITE HYBRID_RST_N 0xFF \\ (addr 0x00) deasert APV reset \\ reset is initally asserted and later deaserted \\ to create a reset pulse for the APV registers END WITH

\\ setting APV registers default values WITH APV_PORT subaddress = 0xFF03 \\ write to registers of all APVs WRITE default values \\ see default values \\ in Slow Control Manual

\\ resync APVs. This will reset the hybrid PLL and readout circuitry of the APVs WITH APVAPP_PORT WRITE (0xFFFFFFFF) 0x0001 \\ force sync reset of all APVs

\\ optional adjust of PLL phase (for longer HDMI cables) WITH APV_PORT subaddress = 0xFF00 \\ all PLLs WRITE CSR1_FINEDELAY phase_value \ 

Setup run mode

The run mode parameters are setup using the ''APV APPLICATION ''port.

APV readout - Zero-suppression mode (APZ) Short description

The signal condition is given by comparing the integral of the signal in a given channel (sum of the pedestal corrected time samples) with the pedestal variation (sigma) of the same channel times the number of samples.

Hence, the processor needs to learn the values of the channel pedestals and pedestal variations (sigma). Also, to guarantee correct operation of the zero-suppression algorithm, the clock phase needs to be adjusted to the correct value. A set of calibration procedures are integrated in the code.

Name CMD Description
CAL_PHASE_SINGLE 0x01 Calibrate clock phase on a single channel.
CAL_PED_SINGLE 0x02 Calibrate pedestal (and sigma), single channel
CAL_FULL_SINGLE 0x03 Calibrate both phase and pedestal (and sigma) values, single channel
CAL_FULL_ALL 0x10 Calibrate all channels enabled by EVBLD_CHENABLE (full calibration). Channels are treated sequentially; current channel being treated is displayed in Calib_all_CRT field of APZ_STATUS register. '''Return to run mode (APZ_CMD = 0) after this command is compulsory'''
CAL_PHASE_ALL 0x11 As above, phase only
CAL_PED_ALL 0x12 As above, pedestal and sigma only

Calibration procedures

The Zero-Suppressor processor needs to learn the pedestal and

-- SorinMartoiu - 22-Apr-2012

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Topic revision: r2 - 2020-08-31 - TWikiAdminUser
 
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