16-CBC3 module

This section is dedicated to the 16CBC3 module received from KIT



2S Module:
  • 2 parallel strip sensors (2 x 1016)
    • 1.8mm sensor spacing
    • 5cm x 90μm cell size
    • sensors are read out by the CMS Binary Chip (CBC). Each CBC reads out 254 strips (2 x 127) and performs hits correlation (stubs) and sends the stub data out at each BX.
  • 2 Front-end hybrids (FEH):
    • Right and Left FEH
      • 8 x CBC3 (Right FEH, FeId="0") + 1 x CIC2 mezzanine card
      • 8 x CBC3 (Left FEH, FeId="1") + 1 x CIC2 mezzanine card
    • CBCs send data to CIC that performs data sparsification, formats the output data, and sends them to the service hybrid (via GBT transmitter)
  • Service hybrid (SEH):
    • Power distribution (DC-DC converters)
    • Data serialization
    • Opto-electrical conversion
    • VTRx (VersatileTransceiver, operating at up to 10 Gb/s in the upstream and up to 5 Gb/s in the downstream directions)
    • GBT (Giga-Bit Transceiver)
    • GBT-SCA (Slow Control Adapter)
More details can be found in slides and share point. Bonus: KIT set-up, DESY set-up

MicroTCA crate: backplane which can accommodate up to 12 Advanced Mezzanine Card (AMC) modules along with up to two μTCA Carrier Hub (MCH) modules.

Current configuration:

  • FC7 ACM card
    • FPGA, Micro SD card slot, 2 FMC connectors for FM-S14 and DIO5
      • FMC (FM-S14)
      • DIO5
  • MCH:
    • system management and Ethernet hub (data transfer to the PC)
uTCA_crate.png FC7_card_2sides.png


Low Voltage

Channel 1 (12V): fan for DC-DC cooling, Channel 2 (10V): module powering + grounding
New_LV.jpeg New_LV_front.jpeg

Power distribution
N.B: For the module, the current must be <1.3A otherwise the SEH will turn off by itself.

High Voltage

Some reference plots from calibration runs.

Remote control

* LV: the NGP800 power supply can be controlled via ChrominiSupervisor (HELP contact Christian Bonnin for details)

  • login to sbg209
  • cd ~/TriDAS/pixel/ChrominiSupervisor
  • ./runChromini.sh
  • leave the terminal open and then point your browser to:
  • go to ChrominiSupervisor > Device Under Test > LV control

  • <img src="
  • N.B: to unlock do Ctrl+Click (Click only won't work)

* HV: the ISEG power supply can be controlled via web interface

  • Point your browser to
  • Note that the IP address is shown on the ISEG device

Data acquisition system

Scintillators -> NIM Logic (Discriminator + Coincidence) -> FC7 (DIO5 + FMC) <-> Module/Ph2_ACF

Ph2_ACF: Phase2 Acquisition & Control Framework

Ph2_ACF is the CMS Tracker Phase2 Acquisition & Control Framework.

The code is already installed on sbgat231 from https://gitlab.cern.ch/cms_tk_ph2/Ph2_ACF.

Get started

I recommend to use the code installed on sbgat231

First of all login to sbgat231 and

cd ~/cms_tk_ph2

You will see the Ph2_ACF code.

Your working directory

Make sure you are in /home/xtaldaq/cms_tk_ph2

cd ~/cms_tk_ph2
mkdir <your username>

In order to be able to run the code from your directory your need to do the following

cd <your username>
ln -s ../Ph2_ACF/settings .
ls -l
The later command will print out: settings -> ../Ph2_ACF/settings (symbolic link).

Important: To remove the symbolic link use: rm -i settings (for safety)

ALERT!: Never use rm -r or rm -f or settings/ (with slash), this will remove the directory or the contents of ../Ph2_ACF/settings.

Parameter setting

Copy the config file to the top-level of your working directory :

cd ~/cms_tk_ph2/<your username>
cp settings/D19CDescription_Cic2.xml ./D19CDescription_Cic2.xml

Open D19CDescription_Cic2.xml with your favorite editor

  • Change the address to uri="chtcp-2.0://sbgat231.in2p3.fr:10203?target="

  • Enable optical link (if disabled, i.e GBT phaseTap="x" enable="0" ) by changing settings to GBT phaseTap="7" enable="1"

Close file.

Other useful settings:

  • Events: <Setting name="Nevents"> 20
  • config files path: CBC_Files path="./settings/CbcFiles/
    • To be update after calibration
  • clock: <Register name="ext_clk_en"> 0
    • 1 -> enable external clock
    • 0 -> disable external clock
  • trigger: <Register name="trigger_source"> 3
    • 3 -> internal trigger (oscillator)
    • 5 -> external trigger
    • 6 -> test pulse (charge injection)

Test the parsing of the D19CDescription_Cic2.xml file

systemtest -f D19CDescription_Cic2.xml

Run the code

At each new terminal enter Ph2_ACF directory and setup the code environment

cd ~/cms_tk_ph2/Ph2_ACF
source setup.sh

Then go back to your working directory:

cd ~/cms_tk_ph2/<your username>

FC7 configuration

Check if the FC7 is connected

ping -c 3

List all available firmware images on the FC7 FPGA

fpgaconfig -c D19CDescription_Cic2.xml -l

Add a new firmware image on the FC7 FPGA

fpgaconfig -c D19CDescription_Cic2.xml -f <your image> -i <name without .bin> 

Load firmware image at each FC7 reboot (current firmware)

fpgaconfig -c D19CDescription_Cic2.xml -i uDTC_2S_CIC2_3Links

Before data-taking

Pedestal equalization and noise measurement (CBC)

feh_2s_test -f D19CDescription_Cic2.xml --withCIC -t -m [-a] [-b]

  • -t : tune offset
  • -m: measure noise
  • -a: all channels at once
  • -b: batch mode

Calibration files are produced in the Results folder. Change the config files path in D19CDescription_Cic2.xml in other to use the obtained ones for data taking.

You will notice that you need to control the power supply to the service hybrid during the power-cycling . At the moment it is done manually (Ph2_ACF pauses to let you do that)


Under Results folder you will find a ROOT file

Noise distribution in the two FEHs
FE0_Noise.png FE1_Noise.png

SCurve for a given CBC

Hit and Stub latency scans with Test Pulse

First of all change trigger settings: <Register name="trigger_source"> 6

Make sure Teste Pulse is enabled: <TestPulse enable="1" polarity="0" amplitude="0x3F" channelgroup="0" delay="0" groundothers="1"/>

To run Hit latency scan, do:

commission -f D19CDescription_Cic2.xml --withCIC -l -m 0 -r 512 -b

  • -m : minimum value
  • -r : range in clock cycles (max=m+r)
  • -l : latency (hits)

To run Stub latency scan 1. add the hit latency found previously under <Settings threshold="550" latency="104"/>

  1. Then run
commission -f D19CDescription_Cic2.xml --withCIC -s -m 0 -r 511 -b

  • -m : minimum value
  • -r : range (max=m+r)
  • -s: stub latency

  1. After you've found the stub latency, add it to
<Register name="common_stubdata_delay"> 5

For test pulse: hit latency = 104 and stub latency = 35.

Hit and Stub latency scans with source/beam

Change trigger settings: <Register name="trigger_source"> 6

And do the same scans as with Test pulse.

  • to find stub latency faster, you can play with external trigger delay <Register name="ext_trigger_delay_value"> 500 .
  • Currently, for external trigger delay = 100, hit latency = 118 and stub latency = 48.

Take data with beam/source

Change trigger settings: <Register name="trigger_source"> 5

Make sure you have updated

  • the config files with ones from calibration
  • the latency values

To take date, run

miniDAQ -f D19CDescription_Cic2.xml --withCIC -e 1000 --dqm --daq mydata.daq

  • -e : number of events
  • --dqm: create histograms
  • --daq: save the data into a binary file (mydata.daq) using the phase-2 Tracker data format
  • -o: output directory. N.B: the directory must be created before (to be fixed)

You can still reproduce qdm histograms from the binary file, just run:

miniSLinkDQM -f mydata.daq --dqm [--tree]


Starting back-end alignment procedure ....
terminate called after throwing an instance of 'std::out_of_range'
  what():  vector::_M_range_check
Abandon (core dumped)
==> Check back-end alignment procedure in tools/BackEndAlignment.cc

I2C readback failed..  for hybrid 0 register 0xa4 [CIC]
terminate called after throwing an instance of 'std::runtime_error'
  what():  I2C readback mismatch...
Abandon (core dumped)
==> Check if you are using CIC2 configuration in your xml file


Document Link
Workshops DAQ, 2S Module
FC7 User Manual FC7 Manual
Micro TCA schroff
d19c userís and developerís manual d19c_manual
CERN, Development of DC-DC converter at CERN dcdc project
The VTRx+, an Optical Link Module for DataTransmission at HL-LHC inspire-prod-file
CBC3 CMSSW indico
CYRCe for CMS Test Beam Preliminary, OT system test meeting, Tracker Plenary during TK Week
CHROMIE tutorial for users indico
Thesis De Clercq, Mykyta, Nikkie

-- EmeryNibigira - 2020-06-08

Topic attachments
I Attachment History Action Size Date Who Comment
PNGpng ChrominiSupervisor_img3.png r1 manage 54.9 K 2020-08-30 - 13:18 EmeryNibigira  
JPEGjpg DSC_0024.JPG r1 manage 6488.8 K 2020-06-12 - 23:25 EmeryNibigira  
PNGpng FC7_card_2sides.png r1 manage 420.7 K 2020-08-30 - 19:27 EmeryNibigira  
PNGpng FE0CBC0_SCurve.png r1 manage 24.2 K 2020-09-14 - 21:12 EmeryNibigira  
PNGpng FE0_Noise.png r1 manage 10.0 K 2020-09-14 - 21:12 EmeryNibigira  
PNGpng FE1_Noise.png r1 manage 8.9 K 2020-09-14 - 21:12 EmeryNibigira  
PNGpng FullModule.png r1 manage 451.7 K 2020-06-14 - 15:13 EmeryNibigira  
PNGpng LV_DC-DC.png r1 manage 20.5 K 2020-06-12 - 23:34 EmeryNibigira  
PNGpng LV_DC-DC_monitoring.png r1 manage 15.4 K 2020-06-13 - 15:06 EmeryNibigira  
PNGpng LV_after.png r1 manage 97.5 K 2020-07-24 - 08:10 EmeryNibigira LV screenshot after some time
PNGpng LV_start.png r1 manage 96.2 K 2020-07-24 - 08:09 EmeryNibigira LV screenshot at the beginning
JPEGjpeg New_LV.jpeg r1 manage 87.8 K 2020-08-30 - 13:18 EmeryNibigira  
JPEGjpeg New_LV_front.jpeg r1 manage 77.3 K 2020-08-30 - 13:18 EmeryNibigira  
PNGpng _FC7_card.png r1 manage 420.7 K 2020-08-30 - 19:25 EmeryNibigira  
PNGpng current_vs_voltage.png r1 manage 9.9 K 2020-07-25 - 16:38 EmeryNibigira  
PNGpng manual_power-cycle.png r1 manage 9.3 K 2020-06-13 - 15:06 EmeryNibigira  
PNGpng noise_vs_voltage.png r1 manage 8.8 K 2020-07-25 - 16:39 EmeryNibigira  
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