16-CBC3 module

This section is dedicated to the 16CBC3 module received from KIT

Set-up

Description

2S Module:
  • 2 parallel strip sensors (2 x 1016)
    • 1.8mm sensor spacing
    • 5cm x 90μm cell size
    • sensors are read out by the CMS Binary Chip (CBC). Each CBC reads out 254 strips (2 x 127) and performs hits correlation (stubs) and sends the stub data out at each BX.
  • 2 Front-end hybrids (FEH):
    • Right and Left FEH
      • 8 x CBC3 (Right FEH, FeId="0") + 1 x CIC1 mezzanine card
      • 8 x CBC3 (Left FEH, FeId="1") + 1 x CIC1 mezzanine card
    • 2 x CIC2 mezzanine cards are available
    • CBCs send data to CIC that performs data sparsification, formats the output data, and sends them to the service hybrid (via GBT transmitter)
  • Service hybrid (SEH):
    • Power distribution (DC-DC converters)
    • Data serialization
    • Opto-electrical conversion
    • VTRx (VersatileTransceiver, operating at up to 10 Gb/s in the upstream and up to 5 Gb/s in the downstream directions)
    • GBT (Giga-Bit Transceiver)
    • GBT-SCA (Slow Control Adapter)
FullModule.png
More details can be found in slides and share point. Bonus: KIT set-up, DESY set-up

Powering

Low Voltage


Power supply: 10V, <1.3A:
DSC_0024.JPG

Power distribution
LV_DC-DC.png


You will notice that you need to control the power supply to the service hybrid during the power-cycling . At the moment it is done manually (Ph2_ACF pauses to let you do that)

manual_power-cycle.png


You will also notice that the Ph2_ACF prints out monitoring values on SEH connected to GBT link

LV_DC-DC_monitoring.png

High Voltage

Read-out

Ph2_ACF: Phase2 Acquisition & Control Framework

Ph2_ACF is the CMS Tracker Phase2 Acquisition & Control Framework.

For prerequisite installation please refer to Installation_of_the_DAQ_software section.

Get the code

git clone https://gitlab.cern.ch/cms_tk_ph2/Ph2_ACF.git
cd Ph2_ACF
source setup.sh

Compile

mkdir build
cd build
cmake ..
make -j6
cd ..

Get started

mkdir rundir
cd rundir 
ln -s ../settings .
Open settings/D19CDescription_Cic.xml

  • Change the address to
    uri="chtcp-2.0://sbgat231.in2p3.fr:10203?target=192.168.7.230:50001"

  • Enable optical link by changing
    <GBT phaseTap="x" enable="0"/>
    to
    <GBT phaseTap="x" enable="1"/>

Close file.

Load firmware image at each FC7 reboot (to be fixed)

fpgaconfig -c settings/D19CDescription_Cic.xml -i d19c_dio5_opto_2h_cic1

Take some calibration

feh_2s_test -f settings/D19CDescription_Cic.xml -b --withCIC

For more details

feh_2s_test -h

References

Document Link
Recent DAQ school indico
FC7 User Manual FC7 Manual
d19c userís and developerís manual d19c_manual
CERN, Development of DC-DC converter at CERN dcdc project
The VTRx+, an Optical Link Module for DataTransmission at HL-LHC inspire-prod-file

-- EmeryNibigira - 2020-06-08

Topic attachments
I Attachment History Action Size Date Who Comment
JPEGjpg DSC_0024.JPG r1 manage 6488.8 K 2020-06-12 - 23:25 EmeryNibigira  
PNGpng FullModule.png r1 manage 451.7 K 2020-06-14 - 15:13 EmeryNibigira  
PNGpng LV_DC-DC.png r1 manage 20.5 K 2020-06-12 - 23:34 EmeryNibigira  
PNGpng LV_DC-DC_monitoring.png r1 manage 15.4 K 2020-06-13 - 15:06 EmeryNibigira  
PNGpng manual_power-cycle.png r1 manage 9.3 K 2020-06-13 - 15:06 EmeryNibigira  
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Topic revision: r17 - 2020-07-02 - EmeryNibigira
 
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