Setups: 4 fibers from router to router checker;

Twinax cable from rim L1DDC to router;

Twinax cable from rim L1DDC to clock;

Router checker: 6V (2A) for voltage and 160MHz clock (pin J15 and J16)

Router (2A) and L1DDC (1A): 10V for voltage

Configure FEBs:

openFELIX_GUI

/afs/cern.ch/user/s/stgcic/public/Opcxml/junk/flx1wedge_SFEB8_6_wo_QS1L3.xml

setupGUI

stgc-dcs

/afs/cern.ch/user/s/stgcic/public/benchtest/baseline/trimmers_x30_Wedge9_th40.json

Load

Make sure prbs disabled

Setup Router and Router checker firmware

Use Jtag to config them

For router checker: using bit_092520_ila40

For router: change modelflag_vector to 53C9, ctrlmod_vio to 3

Router_softrst_vio

For router checker:

Reset using Soft_reset_vio (Active High button) from hw_vios

Hw_ila1,2,3,4

Data: 4bit header followed by 8bit band-id, 5bit phi-id and 6bit BCID

Using 2017.2 Vivado

-- YanlinLiu - 2020-10-09

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Topic revision: r1 - 2020-10-09 - YanlinLiu
 
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