--
FrancescoLicciulli - 2019-09-24
VFAT3 Packaged
This page contains all the technical data and information about the design and the test of the packaged version of the VFAT3 chip.
Organizzations Involved
- INFN - Sezione di Bari: technical management and testing,
- IMEC: design, simulations and production.
VFAT3 Package Design & Production
Design, simulations and production of the package has been assigned to IMEC (
https://www.imec-int.com/en/iclink
) by means of a public price enquiry. The VFAT3 packaging process has been organized into three main steps:
- Package substrate design and simulations.
- Prototypes production.
- Series production.
Regarding to the first step IMEC will provide:
- Design files of the package design compatible with Cadence Allegro Package Designer (.mcm),
- An electrical analysis report including the characteristic impedance of the high-speed nets,
- A thermal analysis report of the package,
- Design guidelines for the PCB.
Package General Description
VFAT3 will be enclosed in a Ball Grid Array (BGA) package with the following specifications:
- Ball Grid Array: 20 x 20 array,
- Ball Grid Array Pitch: 0.8 mm,
- Package size: 17 mm x 17 mm,
- Package material: organic,
- Number of layers of the substrate: 4,
- Thickness of complete assembly at its thickest point: <= 1.6 mm.
Technical Documents
Substrate Design File
For the users that do not use Cadence tools, in order to view the layout of the package substrate Cadence provides a free viewer called "Allegro/OrCAD/SIP/MCM FREE Physical Viewers" that can be downloaded from this link
https://www.cadence.com/content/cadence-www/global/en_US/home/tools/allegro-downloads-start.html
.