############## # For checking PT and SEAM .csv files generated from corresponding .xsl mapping files # This script for mirrorType is updated with some design rules different from the trueType case # due to slot re-assignments # - Z. Yang, Sep. 2017 ############## import csv from collections import Counter ##### Lists for storing each csv file (multi-dimentional) vecSEAM = [] vecPT = [] ##### Read the SEAM0-11.csv and save ALL info to list vecSEAM with open('DCB_mirrorType.csv', 'r') as fSEAM: SEAMReader = csv.DictReader(fSEAM, delimiter=',') #DictReader keys 1st row as header for row in SEAMReader: vecTemp = [] vecTemp.append(row['ref']) vecTemp.append(row['SEAM slot']) vecTemp.append(row['SEAM pin']) vecTemp.append(row['Signal ID']) if (row['Pigtail slot']) != 'None' :# Extract the slot number from the string, eg. 0 from 00 / X-1-F if row['SEAM pin'] != 'H40': # AGND vecTemp.append( str ( int( (str.split( row['Pigtail slot'] ))[0] ) ) ) else: vecTemp.append('') else: vecTemp.append('') #row['Pigtail slot'] if (row['Pigtail pin']) != 'None' : vecTemp.append(row['Pigtail pin']) else: vecTemp.append('') if (row['GBTx ID']) != 'None' : vecTemp.append(row['GBTx ID']) else: vecTemp.append('') if (row['DCB slot']) != 'None':# Extract the slot number from the string, eg 00 / X-0 vecTemp.append( str( int( (str.split( row['DCB slot'] ))[0] ) ) ) else: vecTemp.append('') #row['DCB slot'] if (row['DCB pin']) != 'None' : vecTemp.append(row['DCB pin']) else: vecTemp.append('') ### Add to the vecSEAM list: ####################### ### 0 - ref ### 1 - SEAM slot ### 2 - SEAM pin ### 3 - Signal ID ### 4 - Pigtail slot ### 5 - Pigtail pin ### 6 - GBTx ID ### 7 - DCB slot ### 8 - DCB pin ####################### vecSEAM.append(vecTemp) ##### Read the PT0-11.csv and save ALL info to list vecPT with open('PT_mirrorType.csv', 'r') as fPT: PTReader = csv.DictReader(fPT, delimiter=',') # DictReader keys 1st row as header for row in PTReader: vecTemp = [] vecTemp.append(row['ref']) if row['DCB slot'] != 'None': # Extract the slot number from the string, eg 00/ X-0-F vecTemp.append( str( int( (str.split( row['Pigtail slot'] ))[0] ) ) ) vecTemp.append(row['Pigtail pin']) vecTemp.append(row['Signal ID']) if row['DCB slot'] != 'None': # Extract the slot number from the string, eg 00/ X-0 vecTemp.append( str( int( (str.split( row['DCB slot'] ))[0] ) ) ) else: vecTemp.append('') if row['DCB pin'] != 'None': vecTemp.append(row['DCB pin']) else: vecTemp.append('') if row['GBTx ID'] != 'None': vecTemp.append(row['GBTx ID']) else: vecTemp.append('') ### Add to the vecPT list ####################### ### 0 - ref ### 1 - Pigtail slot ### 2 - Pigtail pin ### 3 - Signal ID ### 4 - DCB slot ### 5 - DCB pin ### 6 - GBTx ID ####################### vecPT.append(vecTemp) ##### Now do checking: #for a in range(0,500): #print vecPT[120][:] #print vecSEAM[2800:3200][:] print( '1). Checking total number of PT/SEAM entries...' ) if len(vecPT)!=4800 : print('Error in total number of PT entries: 4800 !=' + str( len(vecPT)) ) if len(vecSEAM)!=4800 : print('Error in total number of SEAM entries 4800 !='+ str( len(vecSEAM)) ) ##### Check if PT's PT pin matches with SEAM's PT pin print( '2). Checking if PT pin matches between PT.csv and SEAM.csv ...' ) for i in range(0,len(vecPT)): for PTSlot in range(0,12): ## Loop over all 12 PT slots if vecPT[i][1] == str(PTSlot): # on PT, PT slot == PTSlot #print(i) for ii in range(0,len(vecSEAM)): # (SEAM's PT slot == PTSlot ) & (SEAM's SEAM slot matches with PT's DCB) & (SEAM's SEAM pin matches with PT's) if (vecSEAM[ii][4] == str(PTSlot)) and (vecSEAM[ii][1] == vecPT[i][4]) and (vecSEAM[ii][2] == vecPT[i][5]) : #print(ii) if vecSEAM[ii][5] != vecPT[i][2]: # If SEAM's PT pin not match PT's, speak now! #print('vecPT '+str(i) +':'+'('+str(PTSlot)+'-'+str(vecPT[i][2])+')'+str(vecSEAM[ii][5]) +' not match vecSEAM '+str(ii) +':'+'('+str(vecSEAM[ii][1])+'-'+str(vecSEAM[ii][2])+')' +str(vecPT[i][2])) print('vecPT '+str(i) +':'+ str(vecPT[i][:]) +' not match vecSEAM '+str(ii) +':'+ str(vecSEAM[ii][:])) if (vecSEAM[ii][4] == str(PTSlot)) and vecSEAM[ii][5] == vecPT[i][2] and (vecSEAM[ii][2] == vecPT[i][5]) : if (vecSEAM[ii][1] != vecPT[i][4]): # If SEAM's SEAM slot not match with PT's DCB, speak now! print('vecPT '+str(i) +':'+ str(vecPT[i][:]) +' not match vecSEAM '+str(ii) +':'+ str(vecSEAM[ii][:])) if (vecSEAM[ii][4] == str(PTSlot)) and vecSEAM[ii][5] == vecPT[i][2] and (vecSEAM[ii][1] == vecPT[i][4]) : if (vecSEAM[ii][2] != vecPT[i][5]): # If SEAM's SEAM pin not match with PT's, speak now! print('vecPT '+str(i) +':'+ str(vecPT[i][:]) +' not match vecSEAM '+str(ii) +':'+ str(vecSEAM[ii][:])) ##### Check if SEAM's SEAM pin matches with PT's SEAM pin print( '3). Checking if SEAM pin matches between PT.csv and SEAM.csv ...' ) for i in range(0,len(vecSEAM)): for SEAMSlot in range(0,12): ## Loop over all 12 SEAM slots if vecSEAM[i][1] == str(SEAMSlot): # SEAM's SEAM slot == SEAMSlot #print(i) for ii in range(0,len(vecPT)): # (PT's SEAM slot == SEAMSlot ) & (PT's PT slot matches with SEAM's) & (PT's PT pin matches with SEAM's) if (vecPT[ii][4] == str(SEAMSlot)) and (vecPT[ii][1] == vecSEAM[i][4]) and (vecPT[ii][2] == vecSEAM[i][5]) : #print(ii) if vecPT[ii][5] != vecSEAM[i][2]: # If PT's SEAM pin not match SEAM's, speak now! print('vecSEAM '+str(i) +':'+ str(vecSEAM[i][:]) +' not match vecPT '+str(ii) +':'+ str(vecPT[ii][:])) if (vecPT[ii][4] == str(SEAMSlot)) and vecPT[ii][5] == vecSEAM[i][2] and (vecPT[ii][2] == vecSEAM[i][5]) : if (vecPT[ii][1] != vecSEAM[i][4]) : # If PT's PT slot not match SEAM's, speak now! print('vecSEAM '+str(i) +':'+ str(vecSEAM[i][:]) +' not match vecPT '+str(ii) +':'+ str(vecPT[ii][:])) if (vecPT[ii][4] == str(SEAMSlot)) and vecPT[ii][5] == vecSEAM[i][2] and (vecPT[ii][1] == vecSEAM[i][4]) : if (vecPT[ii][2] != vecSEAM[i][5]) : # If PT's PT pin matches with SEAM's, speak now! print('vecSEAM '+str(i) +':'+ str(vecSEAM[i][:]) +' not match vecPT '+str(ii) +':'+ str(vecPT[ii][:])) ##### Check if SEAM's DCB pins match SEAM pins (only exception here is AGND) print( '4). Checking if pins for secondary control between DCBs match...' ) for i in range(0,len(vecSEAM)): for SEAMSlot in range(0,12): ## Loop over all 12 SEAM slots if vecSEAM[i][1] == str(SEAMSlot): # SEAM1's SEAM slot == SEAMSlot for ii in range(0,len(vecSEAM)): # (SEAM2's DCB slot == SEAMSlot ) & (SEAM2's DCB pin matches with SEAM1's SEAM pin) if (vecSEAM[ii][7] == str(SEAMSlot)) and (vecSEAM[ii][8] == vecSEAM[i][2]) : if vecSEAM[i][7] != vecSEAM[ii][1] or vecSEAM[i][8] != vecSEAM[ii][2] : # If SEAM1's DCB slot/pin do not match SEAM2's SEAM slot/pin, speak now! if (vecSEAM[ii][3].split('_')[-2] == 'THERMISTOR') and (vecSEAM[ii][3].split('_')[-1] == 'B'): # If not THERMISTOR_B (which would not fully match AGND, because the N-to-1 matching was negleted when exporting to csv) continue print('vecSEAM '+str(i) +':'+ str(vecSEAM[i][:]) +' not match vecSEAM '+str(ii) +':'+ str(vecSEAM[ii][:])) ##### Check if _N/P on SEAM is also _N/P on PT: print( '5). Checking if _N/P on SEAM is also _N/P on PT...' ) for i in range(0,len(vecPT)): for PTSlot in range(0,12): ## Loop over all 12 PT slots if vecPT[i][1] == str(PTSlot): # select PT's PT slot for ii in range(0,len(vecSEAM)): # (SEAM's PT slot == PTSlot ) & (SEAM's SEAM slot matches with PT's DCB) & (SEAM's SEAM pin matches with PT's) if ( vecSEAM[ii][4] == str(PTSlot) ) and (vecSEAM[ii][1] == vecPT[i][4] ) and ( vecSEAM[ii][2] == vecPT[i][5] ) : # Look for signal ID w/ "_N/P" if ( vecPT[i][3].split('_')[-1] == 'P' ) or ( vecPT[i][3].split('_')[-1] == 'N' ): # But does not inlude {thermistor, RESET, SCL, SDA} if (vecPT[i][3].split('_')[-2]) not in {'THERMISTOR', 'RESET', 'SCL', 'SDA'}: # If _N/P do not match on PT and SEAM, speak now! if ( vecPT[i][3].split('_')[-1] != vecSEAM[ii][3].split('_')[-1] ): print('vecPT '+str(i) +':'+ str(vecSEAM[ii][5]) +' not match vecSEAM '+str(ii) +':'+ str(vecPT[i][2])) ##### Check if SEAM's PT pin repeats within each PT slot: print( '6). Checking if PT pin on SEAM.csv repeats within each PT slot...' ) for PTSlot in range(0,12): # Loop over 12 available PT slots listForCounter = [] for i in range(0, len(vecSEAM)): if ( vecSEAM[i][4] != str(PTSlot) ) or ( vecSEAM[i][5] =='' ):# Skip if not the (same) PT slot, or if no PT pin continue listForCounter.append(vecSEAM[i][4]+vecSEAM[i][5]) # At the end of each PT slot loop, count the valid PT pin list counted = Counter(listForCounter) for pin, freq in counted.items(): if (freq > 1) and (pin != ''): print(pin,freq, PTSlot) ##### Check if SEAM's DCB pin repeats within each SEAM slot: print( '7). Checking if DCB pin on SEAM.csv repeats within each SEAM slot...' ) for SEAMSlot in range(0,12): # Loop over 12 available SEAM slots listForCounter = [] for i in range(0, len(vecSEAM)): # Skip if not the (same) SEAM slot, or if no SEAM pin if ( vecSEAM[i][7] != str(SEAMSlot) ) or ( vecSEAM[i][8] =='' ): continue listForCounter.append(vecSEAM[i][8]) # At the end of each PT slot loop, count the valid PT pin list counted = Counter(listForCounter) for pin, freq in counted.items(): if (freq > 1) and (pin != 'H40'): # SEAM pin H40 is AGND print(pin,freq, SEAMSlot) ##### Check if PT's SEAM pin repeats within each SEAM slot: print( '8). Checking if SEAM pin on PT.csv repeats within each SEAM slot...' ) for SEAMSlot in range(0,12): # Loop over 12 available SEAM slots listForCounter = [] for i in range(0, len(vecPT)): # Skip if not the (same) SEAM slot, or if no SEAM pin if ( vecPT[i][4] != str(SEAMSlot) ) or ( vecPT[i][5] =='' ): continue listForCounter.append(vecPT[i][5]) # At the end of each SEAM-slot loop, count the valid SEAM pin list counted = Counter(listForCounter) for pin, freq in counted.items(): if (freq > 1) and (pin != 'H40'): # SEAM pin H40 is AGND print(pin,freq, SEAMSlot) #### Check if PT's Signal ID agrees w/ SEAM's Signal ID print( '9). Checking if Signal IDs match between PT.csv and SEAM.csv ...' ) for i in range(0,len(vecPT)): for PTSlot in range(0,12): ## Loop over all 12 PT slots if vecPT[i][1] == str(PTSlot): # select PT's PT slot for ii in range(0,len(vecSEAM)): # (SEAM's PT slot == PTSlot ) & (SEAM's SEAM slot matches with PT's DCB) & (SEAM's SEAM pin matches with PT's) if ( vecSEAM[ii][4] == str(PTSlot) ) and (vecSEAM[ii][1] == vecPT[i][4] ) and ( vecSEAM[ii][2] == vecPT[i][5] ) : ## Look for signal ID types of the following: # 1. P_ASIC - DC_ELK: if ( vecPT[i][3].split('_')[1] == 'ASIC' ) : # If Signal IDs do not match between PT and SEAM, speak now! if ( vecSEAM[ii][3].split('_')[1] != 'ELK' ): print('Sig ID: '+'vecPT '+str(i) +':'+ str(vecSEAM[ii][5]) +' not match vecSEAM '+str(ii) +':'+ str(vecPT[i][2])) # 2. P_(EAST_)TFC - MC_TFC: elif ( vecPT[i][3].split('_')[-2] == 'TFC' ): # If Signal ID on SEAM is not MC_TFC#: if ( 'TFC' not in vecSEAM[ii][3].split('_')[1] ): print('Sig ID: '+'vecPT '+str(i) +':'+ str(vecSEAM[ii][5]) +' not match vecSEAM '+str(ii) +':'+ str(vecPT[i][2])) # 3. P_(WEST_)CLK - DC_OUT_RCLK# elif ( vecPT[i][3].split('_')[-2] == 'CLK' ): # If Signal ID on SEAM is not DC_OUT_RCLK: if ( 'DC_OUT_RCLK' not in vecSEAM[ii][3] ): print('Sig ID: '+'vecPT '+str(i) +':'+ str(vecSEAM[ii][5]) +' not match vecSEAM '+str(ii) +':'+ str(vecPT[i][2])) # 4. P_RESET - EC_RESET_GPIO: elif ( vecPT[i][3].split('_')[-2] == 'RESET' ): if ( 'EC_RESET_GPIO' not in vecSEAM[ii][3] ): print('Sig ID: '+'vecPT '+str(i) +':'+ str(vecSEAM[ii][5]) +' not match vecSEAM '+str(ii) +':'+ str(vecPT[i][2])) # 5. P_I2C_SCL/SDA - EC_HYB_i2C_SCL/SDA elif ( vecPT[i][3].split('_')[-3] == 'I2C' ): if ( vecSEAM[ii][3].split('_')[-2] != vecPT[i][3].split('_')[-2] ): print('Sig ID: '+'vecPT '+str(i) +':'+ str(vecSEAM[ii][5]) +' not match vecSEAM '+str(ii) +':'+ str(vecPT[i][2])) # 6. P_THERMISTOR - EC_ADC (_B connects to AGND ) elif ( vecPT[i][3].split('_')[-2] == 'THERMISTOR' ) and ( vecPT[i][3].split('_')[-1] == 'A' ): if ( 'EC_ADC' not in vecSEAM[ii][3] ): print('Sig ID: '+'vecPT '+str(i) +':'+ str(vecSEAM[ii][5]) +' not match vecSEAM '+str(ii) +':'+ str(vecPT[i][2])) ##### Check the Elink Packing Order between DC_ELK and ASIC_CH, according to the GBTx-DCB Eport Assignment print('10). Check the Elink Packing Order between DC_ELK and ASIC_CH, according to the GBTx-DCB Eport Assignments document ...') ## Loop over PT slots 0-11 for PTSlot in range(0,12): for numP in range(1,5): # loop over P 1-4 (hybrids) for numAsic in range(0,8): # loop over ASIC 0-7 packingList = [] # A List for every ASIC, of ELK - ASIC channels for i in range(0,len(vecPT)): # select PT's PT slot; and select P_ASIC_CH signal type; Looking at P (or N) only if vecPT[i][1] == str(PTSlot) and ( 'ASIC' in vecPT[i][3] ) and (vecPT[i][3].split('_')[4] == 'P') : # Look at the selected CH's on the same P# and ASIC#, if int( filter(str.isdigit, vecPT[i][3].split('_')[0]) ) == numP and int( vecPT[i][3].split('_')[2] ) == numAsic: for ii in range(0, len(vecSEAM)): ## MATCHING PINS: (SEAM's PT slot == PTSlot ) & (SEAM's SEAM slot matches with PT's) & (SEAM's SEAM pin matches with PT's) if ( vecSEAM[ii][4] == str(PTSlot) ) and ( vecSEAM[ii][1] == vecPT[i][4] ) and ( vecSEAM[ii][2] == vecPT[i][5] ) : ## Append ELK, ASIC channel numbers packingList.append( [ int(filter(str.isdigit,vecPT[i][3].split('_')[3])), int(filter(str.isdigit, vecSEAM[ii][3].split('_')[2])) ] ) #print(packingList) if len(packingList) != 0: refELK = packingList[0][1] # This should be the ELK with the largest number (ASIC_CH0) ## verify the starting ELK (largest ELK channel number) for each ASIC for 3/4/5 elink pack if len(packingList) == 3: ## For 3 elink pack: if refELK not in [11,8,6,5,2]: print('Elink order error (3-elink) in: '+'PTSlot/HybridP/ASIC '+str(PTSlot)+'/'+str(numP)+'/'+str(numAsic) ) elif len(packingList) == 4: ## For 4 elink pack: if refELK not in [11,6]: print('Elink order error (4-elink) in: '+'PTSlot/HybridP/ASIC '+str(PTSlot)+'/'+str(numP)+'/'+str(numAsic) ) elif len(packingList) == 5: ## For 5 elink pack: if refELK not in [11,6]: print('Elink order error (5-elink) in: '+'PTSlot/HybridP/ASIC '+str(PTSlot)+'/'+str(numP)+'/'+str(numAsic) ) else: print('Elink order error (# of elink) in: '+'PTSlot/HybridP/ASIC '+str(PTSlot)+'/'+str(numP)+'/'+str(numAsic) ) ## Check that with ASIC channel number increasing by 1 (++), ELK channel number decreases by 1 (--) for ch in range(0,len(packingList)): # Check that with increasing (++) ASIC channel number, ELK channel number decreases (--) if packingList[ch][1] != (refELK - ch): #continue print('Elink order error (++/--) in: '+'PTSlot/HybridP/ASIC '+str(PTSlot)+'/'+str(numP)+'/'+str(numAsic) ) ####### [OLD] Check MC_OUT_RCLK to DC_IN_RCLK, according to design rules in the Documentation ##for i in range(0,len(vecSEAM)): ## for SEAMSlot in range(0,12): ## ## Loop over all 12 SEAM slots ## if vecSEAM[i][1] == str(SEAMSlot) and ( 'MC_OUT' in vecSEAM[i][3] ) and len(vecSEAM[i][8]) != 0: # select SEAM's SEAM slot and Sig ID MC_OUT ## SeamSlot = int(vecSEAM[i][1]) ## DcbSlot = int(vecSEAM[i][7]) ## # DCBs(0,1,4,5,6,7,8,9) with Masters 0,1,6,7,8 ## if SeamSlot in [0,1,6,7,8]: ## if DcbSlot not in [0,1,4,5,6,7,8,9]: ## print('MC_OUT error in DCBs(0,1,4,5,6,7,8,9) with Masters 0,1,6,7,8') ## # DCB(9,10,11) with Masters 9,10 (plus 4 from 8,9) ## elif SeamSlot in [9,10]: ## if DcbSlot not in [8,9,10,11]: ## print('MC_OUT error in DCB(9,10,11) with Masters 9,10') ## # DCB(2,3,4,5) with Masters 4,5 ## elif SeamSlot in [4,5]: ## if DcbSlot not in [2,3]: ## print('MC_OUT error in DCB(2,3,4,5) with Masters 4,5') ## else: ## print('Non-master used for MC_OUT') ## ##### Check MC_SEC to EC_SEC, according to design rules in the Documentation print('11). Check MC_SEC to EC_SEC, according to design rules in the Documentation ...') for i in range(0,len(vecSEAM)): for SEAMSlot in range(0,12): ## Loop over all 12 SEAM slots if vecSEAM[i][1] == str(SEAMSlot) and ( 'MC_SEC' in vecSEAM[i][3] ) and len(vecSEAM[i][8]) != 0: # select SEAM's SEAM slot and Sig ID MC_SEC SeamSlot = int(vecSEAM[i][1]) DcbSlot = int(vecSEAM[i][7]) # DCBs(0,1,4,5,6,7,8,9) with daisy-chain MC -> EC if SeamSlot in [0,1,4,5,6,7,8,9]: index = -1 for j in range(0,8): if SeamSlot == [0,1,4,5,6,7,8,9][j]: index = j if (index != 7) and DcbSlot != [0,1,4,5,6,7,8,9][index+1]: print('MC_SEC error in DCBs(0,1,6,7,8) with Masters 0,1,6,7,8') if (index == 7) and DcbSlot != [0,1,4,5,6,7,8,9][index-7]: print('MC_SEC error in DCBs(0,1,6,7,8) with Masters 0,1,6,7,8') # DCB(10,11) elif SeamSlot in [10,11]: if DcbSlot not in [10,11]: print('MC_SEC error in DCB(10,11) with Masters 10,11') # DCB(2,3) with Masters 2,3 elif SeamSlot in [2,3]: if DcbSlot not in [2,3]: print('MC_SEC error in DCB(2,3) with Masters 2,3') else: print('Non-master used for MC_SEC') ##### Check MC_TFC to Hybrids, according to design rules in the Documentation print('12). Check Hybrid TFC, according to design rules in the Documentation ...') ## GBT number - control channel ordering: GBTList = (6,1,2,3,4,5) TFCList = ('H34','H30','H6','H2','F2','B2') # (_P)CH numbers 5,4,3,2,1,0 for i in range(0,len(vecPT)): for PTSlot in range(0,12): ## Loop over all 12 PT slots # select PT's PT slot and Sig ID P_TFC with valid SEAM pin, and only _P to avoid double-counting if vecPT[i][1] == str(PTSlot) and ( 'TFC' in vecPT[i][3] ) and vecPT[i][3].split('_')[-1] == 'P' and len(vecPT[i][5]) != 0: SeamSlot = int(vecPT[i][4]) if vecPT[i][3].split('_')[-3] != "WEST": # depending on the 4-ASIC group type (EAST/WEST), find its DCB slot HybridDCBSlot = int(vecPT[(i-41)][4]) # (i-41) should select a P_ASIC_x_CH0 entry, in order to get the DCB slot of the ASIC being read out if SeamSlot != HybridDCBSlot: # Check that the control sig is from the DCB to which the ASIC group transmit data print('TFC error in PT-'+str(PTSlot)+'; Sig ID: '+str(vecPT[i][3])) GBTxNum = int(vecPT[(i-41)][6][-1]) #if vecPT[(i-57)][6][-1] != vecPT[(i-41)][6][-1]:## for the 2-GBTx case, for which the highe-numbered control CH is used #GBTxNum = max( int(vecPT[(i-57)][6][-1]), int(vecPT[(i-41)][6][-1]) ) for j in range(0,6): if GBTxNum == GBTList[j]: ### Now check the GBT - control channel order: if vecPT[i][5] != TFCList[j]: # for the 2-GBTx case, for which the highe-numbered control CH is used if len(vecPT[(i-57)][6]) >= 6 and int(vecPT[(i-57)][6][-1]) != int(vecPT[(i-41)][6][-1]): if vecPT[i][5] == TFCList[j-1]: break print('TFC error in PT-'+str(PTSlot)+'; Sig ID: '+str(vecPT[i][3])) break if vecPT[i][3].split('_')[-3] == "WEST": HybridDCBSlot = int(vecPT[(i-117)][4]) # (i-117) should select a P_ASIC_x_CH0 entry, in order to get the DCB slot of the ASIC being read out if SeamSlot != HybridDCBSlot: # Check that the control sig is from the DCB to which the ASIC group transmit data print('TFC error in PT-'+str(PTSlot)+'; Sig ID: '+str(vecPT[i][3])) ####### [OLD] Check MC_TFC to Hybrids, according to design rules in the Documentation ### Counters for checking the total number of signals ##counterTFC1 = 0 ##counterTFC2 = 0 ##counterTFC3 = 0 ##for i in range(0,len(vecSEAM)): ## for SEAMSlot in range(0,12): ## ## Loop over all 12 SEAM slots ## # select SEAM's SEAM slot and Sig ID MC_TFC with valid PT pin, and only _P to avoid double-counting ## if vecSEAM[i][1] == str(SEAMSlot) and ( 'MC_TFC' in vecSEAM[i][3] ) and vecSEAM[i][3].split('_')[-1] == 'P' and len(vecSEAM[i][5]) != 0: ## SeamSlot = int(vecSEAM[i][1]) ## PtSlot = int(vecSEAM[i][4]) ## # DCBs(0,1,6,7,8) to 28 sigs on PT[0:7]; ## if SeamSlot in [0,1,6,7,8]: ## if PtSlot in [0,1,2,3,4,5,6,7]: ## counterTFC1 = counterTFC1 + 1 ## elif PtSlot in [10,11]: # was 8,9 ## continue ## else: ## print('TFC error in DCBs(0,1,6,7,8) with Masters 0,1,6,7,8') ## # DCB(9,10) to 12 sigs on PT[0:7], ## elif SeamSlot in [9,10]: ## if PtSlot in [8,9,10,11]: ## counterTFC2 = counterTFC2 + 1 ## else: ## print('TFC error in DCB(9,10) with Masters 9,10') ## # DCB(4,5) to depopulated hybrids: check that exactly 12 used ## elif SeamSlot in [4,5]: ## counterTFC3 = counterTFC3 + 1 ## else: ## print('Non-master used for MC_TFC') ##if counterTFC1 != 28: ## print('TFC error in DCBs(0,1,6,7,8): ' + str(counterTFC1)) ##if counterTFC2 != 12: ## print('TFC error in DCB(9,10): '+ str(counterTFC2)) ##if counterTFC3 != 12: ## print('TFC error in DCB(4,5) for 12 depop hybrids: '+ str(counterTFC3)) ## ####### Check DC_OUT_RCLK (from DCs to Hybrids) ##for i in range(0,len(vecSEAM)): ## for SEAMSlot in range(0,12): ## ## Loop over all 12 SEAM slots ## if vecSEAM[i][1] == str(SEAMSlot) and ( 'DC_OUT_RCLK' in vecSEAM[i][3] ) and len(vecSEAM[i][5]) != 0: # select SEAM's SEAM slot and Sig ID DC_OUT ## SeamSlot = int(vecSEAM[i][1]) # SEAM slot of the DC ## PtSlot = int(vecSEAM[i][4]) # PT slot of the hybrid ## # DCBs(0,1,6,7,8) to PT[0:7], all 40 including all the depopulated. ## if SeamSlot in [0,1,6,7,8]: ## if PtSlot not in range(0,8): ## print('DC_OUT error in DCBs(0,1,6,7,8) with Masters 0,1,6,7,8') ## # DCB(9,10) to PT[8:11] ## elif SeamSlot in [9,10]: ## if PtSlot not in range(8,12): ## print('DC_OUT error in DCB(9,10) with Masters 9,10') ## # DCB(4,5) with Masters 4,5 ## elif SeamSlot in [4,5]: ## if PtSlot is not None: ## print('DC_OUT error in DCB(4,5) with Masters 4,5') ## else: ## print('Non-master used for DC_OUT') ## ####### Check EC_RESET to DC and Hybrids, according to design rules in the Documentation ### Counters for checking the total number of signals ##counterDcReset = 0 ##counterPReset = 0 ##for i in range(0,len(vecSEAM)): ## for SEAMSlot in range(0,12): ## ## Loop over all 12 SEAM slots ## # select SEAM's SEAM slot and Sig ID EC_RESET with valid PT pin ## if vecSEAM[i][1] == str(SEAMSlot) and ( 'EC_RESET' in vecSEAM[i][3] ) and (len(vecSEAM[i][5])!=0 or len(vecSEAM[i][8])!=0): ## # slot numbers with initial value -1 for checking ## PtSlot = -1 ## DcbSlot = -1 ## if len(vecSEAM[i][5])!=0: ## PtSlot = int(vecSEAM[i][4]) ## if len(vecSEAM[i][8])!=0: ## DcbSlot = int(vecSEAM[i][7]) ## if len(vecSEAM[i][5]) !=0 and len(vecSEAM[i][8]) !=0: ## print('same EC_RESET used on both PT and SEAM') ## # DCBs(0,1,6,7,8) to 40 Hybrid sigs on PT[0:7] and 8 DC sigs on DCB(0,1,4,5,6,7,8,9) ## if SEAMSlot in [0,1,6,7,8]: ## if PtSlot in range(0,8): ## counterPReset = counterPReset + 1 ## elif DcbSlot in [0,1,4,5,6,7,8,9]: ## counterDcReset = counterDcReset + 1 ## else: ## print('EC_RESET error in DCBs(0,1,6,7,8) with SCA 0,1,6,7,8') ## # DCB(9,10) to 14 Hybrid sigs on PT[8:11], and 2 DC sigs on DCB(10,11) ## elif SEAMSlot in [9,10]: ## if PtSlot in [8,9,10,11]: ## counterPReset = counterPReset + 1 ## elif DcbSlot in [10,11]: ## counterDcReset = counterDcReset + 1 ## else: ## print('EC_RESET error in DCB(9,10) with SCA 9,10') ## # DCB(4,5) used 1 EC_RESET on each SCA, for 2 DC_RESET sigs on DCB(2,3) ## elif SEAMSlot in [4,5]: ## if DcbSlot in [2,3]: ## counterDcReset = counterDcReset + 1 ## else: ## print('EC_RESET error in DCB(4,5) with SCA 4,5') ## else: ## print('Non-SCA used for EC_RESET') ##if counterPReset != 54: ## print('EC_RESET error in P_RESET #: ' + str(counterPReset)) ##if counterDcReset != 12: ## print('EC_RESET error in DC_RESET #: '+ str(counterDcReset)) ## ####### Check EC_HYB_i2C (from SCA to Hybrids) ##for i in range(0,len(vecSEAM)): ## ## Loop over all 12 SEAM slots ## for SEAMSlot in range(0,12): ## ## # select SEAM's SEAM slot and Sig ID EC_HYB_i2C (and PT pin exists) ## if vecSEAM[i][1] == str(SEAMSlot) and ( 'EC_HYB_i2C' in vecSEAM[i][3] ) and len(vecSEAM[i][5]) != 0: ## SeamSlot = int(vecSEAM[i][1]) # SEAM slot of the DC ## PtSlot = int(vecSEAM[i][4]) # PT slot of the hybrid ## # DCBs(0,1,6) to PT[0:7] ## if SeamSlot in [0,1,6]: ## if PtSlot not in range(0,8): ## print('EC_HYB_I2C error in DCBs(0,1,6)') ## # DCB(9) to PT[8:11] ## elif SeamSlot in [9]: ## if PtSlot not in range(8,12): ## print('EC_HYB_I2C error in DCB(9)') ## else: ## print('Non-SCA used for EC_HYB_I2C') ## ####### Check EC_DC_i2C on SCA to DC_i2C on DC, according to design rules in the Documentation ##for i in range(0,len(vecSEAM)): ## for SEAMSlot in range(0,12): ## ## Loop over all 12 SEAM slots ## if vecSEAM[i][1] == str(SEAMSlot) and ( 'EC_DC_i2C' in vecSEAM[i][3] ) and len(vecSEAM[i][8]) != 0: # select SEAM's SEAM slot and Sig ID EC_DC_i2C ## SeamSlot = int(vecSEAM[i][1]) ## DcbSlot = int(vecSEAM[i][7]) ## if SeamSlot in [0]: ## if DcbSlot not in [0]: ## print('EC_DC error in DCB(0)') ## elif SeamSlot in [1]: ## if DcbSlot not in [1]: ## print('EC_DC error in DCB(1)') ## elif SeamSlot in [4]: ## if DcbSlot not in [2]: ## print('EC_DC error in DCB(4)') ## elif SeamSlot in [5]: ## if DcbSlot not in [3]: ## print('EC_DC error in DCB(5)') ## elif SeamSlot in [6]: ## if DcbSlot not in [4,6]: ## print('EC_DC error in DCB(6)') ## elif SeamSlot in [7]: ## if DcbSlot not in [5,7]: ## print('EC_DC error in DCB(7)') ## elif SeamSlot in [8]: ## if DcbSlot not in [8,9]: ## print('EC_DC error in DCB(8)') ## elif SeamSlot in [10]: ## if DcbSlot not in [10,11]: ## print('EC_DC error in DCB(10)') ## else: ## print('SCA assignment for EC_DC_i2C not agree with Documentation') ## ####### Check EC_ADC to DCB/Hybrid thermistors DC/OM_Thermistor ##for i in range(0,len(vecSEAM)): ## for SEAMSlot in range(0,12): ## ## Loop over all 12 SEAM slots ## # select SEAM's SEAM slot and Sig ID EC_ADC with valid PT pin ## if vecSEAM[i][1] == str(SEAMSlot) and ( 'EC_ADC' in vecSEAM[i][3] ) and (len(vecSEAM[i][5])!=0 or len(vecSEAM[i][8])!=0): ## # slot numbers with initial value -1 for checking ## PtSlot = -1 ## DcbSlot = -1 ## if len(vecSEAM[i][5])!=0: ## PtSlot = int(vecSEAM[i][4]) ## if len(vecSEAM[i][8])!=0: ## DcbSlot = int(vecSEAM[i][7]) ## if len(vecSEAM[i][5]) !=0 and len(vecSEAM[i][8]) !=0: ## print('same EC_ADC used on both PT and SEAM') ## ## According to Documentation, DCBs(0,1,4,5,6,7,8,9,10) to 54 Hybrid sigs on PT and 20 DC sigs on DCB(0,1,4,5,6,7,8,9,10,11) ## if SEAMSlot in [0]: ## if PtSlot not in [2,3] and DcbSlot not in [0]: ## print('EC_ADC error in DCB(0)') ### print(PtSlot, DcbSlot) ## elif SEAMSlot in [1]: ## if PtSlot not in [0,1] and DcbSlot not in [1]: ## print('EC_ADC error in DCB(1)') ## elif SEAMSlot in [4]: ## if PtSlot != -1 and DcbSlot not in [2]: ## print('EC_ADC error in DCB(4)') ## elif SEAMSlot in [5]: ## if PtSlot != -1 and DcbSlot not in [3]: ## print('EC_ADC error in DCB(5)') ## elif SEAMSlot in [6]: ## if PtSlot not in [6,7] and DcbSlot not in [4,6]: ## print('EC_ADC error in DCB(6)') ## elif SEAMSlot in [7]: ## if PtSlot not in [4,5] and DcbSlot not in [5,7]: ## print('EC_ADC error in DCB(7)') ## elif SEAMSlot in [8]: ## if PtSlot != -1 and DcbSlot not in [8,9]: ## print('EC_ADC error in DCB(8)') ## elif SEAMSlot in [9]: ## if PtSlot not in [10,11] and DcbSlot != -1: ## print('EC_ADC error in DCB(9)') ## elif SEAMSlot in [10]: ## if PtSlot not in [8,9] and DcbSlot not in [10,11]: ## print('EC_ADC error in DCB(10)') ## else: ## print('SCA assignment for EC_ADC not agree with Documentation')